Study And Implement On The Key Technologies Of The Loop Engine On Array Processor

The development of circuit integration greatly promotes renovation of computer architecture. Considering wire delay, clock frequency, cost of design and validation, multithreading parallelism is polupar used, especially the one chip multiprocessors architecture, according to it's simple and high efficiency.The Loop Engine on Array Processors (LEAP) ,which raised fixed instruction multiple data model to accelerate loop program,is a one chip-multiprocessors(CMP) architecture. Now LEAP's study is just beginning, the paper will outspread researches aimed at three key techniques .For CMP architecture, the memory accessing speed affects the whole performing efficiency.In this paper we have a detailed study of the memory models,hierarchical Cache designs,organizations for the address space, communication models and some new cache design technologies, and then bring forward the design project of the LEAP's memory system.Considering about LEAP's specialties,we adopt the data packed technology and prefetch according to memory accessing's rule.Through running FFT on FPGA,it is proved that the technology can effectively reduce the memory accessing's delay, economize memory width.Aiming at the shortage that the old LEAP can only run single-layer loop,which greatly limit the kinds of programs it can reform,we will enhance the LEAP to run multi-layers loop.In this paper we study the data hazards and control hazards in loop, ameliorating the old code to realize the automatic performing of multi-layers loop.Carrying out the realizing and optimizing of hardware on FPGA.Optimizing the old PE code to enonomize circuit components, the code being optimized can be synthesized without any compoments redundancy.Finally, combining the three parts,we run FIR programs, and synthesize on Virtex2 chip of Xilinx company.