Study Of Chip Multiprocessors Applied To Aerospace

This dissertation focuses on the research of the parallel and fault tolerant CMP (ChipMultiprocessors) applied to aerospace on the background of Beijing MicroelectronicsTechnology Institute "10.5" Research Project about fault tolerant processor. The theoryof CMP is systematically studied. The main research works and creative contributions ofthis dissertation are as follows:1. As a chief member, the author has accomplished the design of 32-bit RISC BM3801processor with fault tolerance based on SPARC V8 architecture. The chip has beentapped out successfully in 0.18um SMIC technology. The chip dissipates 180roW, and itsdie area occupies 5×5mm~2. The chip area occupies 4.5×4.5cm~2.2. A optimal liner fitting method by subsection convergence is proposed to gain theinitial iterative value for division and square root algorithms. The circuit area that gainsthe initial value is only 2/3 of ROM look-up's which is based on Goldschmidt divisionand square root algorithms. The performance of the double precision division is 1.8 timesfaster than Radix-16 SRT's.3. A novel method which could accomplish the processor of Transcendental Functionsthrough the single hardware circuit is studied. The processor could calculatetrigonometric function, hyperboloidal function, exponential function, and logarithmfunction. Its area is small and its energy consuming is controllable.4. A dynamic configurable architecture with 2 processors on a chip is proposed for thedifferent aerospace application field or different flight course of the space aircraft. Itcould run in parallel by dynamic configuration for high performance. On the other hand,it could run in redundancy by two processors for high fault tolerance. While there arepermanent errors which occur on one processor, it is degraded to run only by anotherprocessor so as to fulfill the important mission continually.5. A two-level fault-tolerance architecture is proposed. In the bottom level, theevery processor is error detection and correction. In the upper level, it runs in redundancyby the two processors for fault tolerance. It can enhance the ability of error detection andcorrection evidently and the errors could be corrected inside pipeline of the processors. Itcan detect and check single error which occurs in the serial circuits, multi-errors whichoccur in the different registers or caches, and the instantaneous errors which occur in thecombination circuits. The errors could be corrected during 5-25 cycles. Contrarily, asingle processor with EDAC could only correct the single error. In the redundancy modeby the two processors without EDAC, it has to take thousands of cycles to correct the errors and could not correct the errors which occur in the shared RAM by the twoprocessors.6. A novel method of a transmitting message based on priority is studied, based onmodified fat tree of Minsky's RN1. It could reduce the probability of the messageslivelock when a congestion occurs in the interconnect network. On the other hand, thetechnique of message transmitting based on idempotent message is accomplished toimprove the dependability about the message transmitting.