VHDL Compiling System Design Methods And Studies On The Key Techniques

VHDL is a national industry standard that U.S.A affirms, already a lot of countries and regions have got fast popularization and application in the world now. VHDL can abstractly express circuit's structure and behavior in formalization, it also sustains arrangement and domain's description in logic design. VHDL borrows the description of high-level language's ingenious configuration, with which it can refine circuit description. VHDL has circuit simulation and validation mechanism, which makes it can assure the correctness of design and sustain the synthesis transform of circuit description from high-level to low-level. It is easy to manage files and reuse the design. So it has distinctive meaning to make VHDL as the input language in high-level synthesis, because it can combine the virtue of it as industry standard and high-level synthesis itself.The same as traditional advanced programming languages' compiling system, the compiling system of VHDL language has a very important position too. It has important influence on the realization and performance of the whole high-level synthesis and mix simulation system. However, there is almost no detailed explaining on VHDL lexical analysis and grammatical analysis generation in IC high-level synthesis theory research, while they are just the key techniques which can influence the whole compiling system. So it is necessary to have a deepparticular research on them. Because there are not a lot of materials in this respect, it is very difficult in surveying and studying earlier stage. It needs great efforts to move ahead a little.This paper puts the emphasis on the deep studies of the distilling of VHDL language algorithm-level subset, realization of lexical analyzer and parser analyzer. All of them are important for VHDL compiling system design.A conspectus of digital system design and high-level synthesis are presented first in this paper. It briefly introduces compiling theory, compiling program's structure and VHDL language's history and usage. Its purpose is to give the reader a whole understanding of the issues of VHDL compiling system.Then, tnis paper focus on the research of VHDL compiling system design. Here, the writer uses a new software named Parser Generator2.0, this software is easier for using than previous software and it can be installed and run under Windows OS.Studies on several key techniques in VHDL compiling system design are then discussed in turn. Distilling a subset of VHDL language is very important for the generation of lexical analyzer. Because VHDL language itself is based on simulation, all the means it provides are used to build simulation models., so there is a translate procedure when it is synthesized. The paper has a detailed research on VHDL subset distilling and lexical analyzer designing. And the lexical analysis generation program is given in appendix.Finally, the paper discusses the most important part in VHDL compiling system, that is the designing and realization of parser analyzer. Combined with the writer's development experience, several design tactics are listed in detail. Especially discusses the resolving of conflict.