Research On The Approach To Compile Programming Language Into VHDL Behavioral Description

VHDL is a language for the description of digital hardware system, and C is a high level programming language for coding sequential statements. Because C is well-structured and easily-extended, when C code being compiled to VHDL code, using sequential C language to model circuits in VHDL with concurrent characterization, can reduce time and complexity of designing on digital system. In this thesis, the approach to compile programming language into VHDL behavioral description is studied. The method of making CDFG to be intermediate representation is presented, then the experiment on the method is carried out, the translated VHDL code is performed by simulation, and the result of experiment is analyzed.Firstly, VHDL and the difference of C and VHDL is introduced, compile techniques and its status are given. The overall design plan of this thesis is presented briefly.Secondly, the compiling process of the compiling method in this thesis is discussed in detail. In order to explain the process of the compile techniques, a gradual study process is given: first, lexical analysis and grammar analysis are discussed; second, based on grammar analysis, the processes from AST to CDFG and from CDFG to VHDL code are given. The method of generating CDFG based on AST is studied in detail.Finally, input the C code, the compiling C to VHDL is carried out by using the presented method of this thesis successfully, and the translated VHDL code is evaluated in simulation software. The result of experiment show that the compile method is effective in C to VHDL.