Design And Implementation Of General Instruction Set Description Language

System simulator has been a significant tool for embedded system developers in the field of hardware design, system software and application software development. With a proper simulation platform, developers are capable to run, debug and verify embedded system software of different architectures in a virtual environment. Therefore computer system simulators have entered the spotlight of both academia and industry.The development of computer system simulator is a complex engineering process, and most of its developing efforts(80%) are spent on the instruction set simulation subsystem, which is the main focus of this paper. Following a comprehensive survey of most popular instruction set architecture (ISA) description languages, this thesis presents Smart-ISDL- a light-weight ISA description language. Smart-ISDL is a general purpose ISA description language, which is capable of describing various ISA, such as ARM, MIPS, 8051 and so on. Smart-ISDL uses a simple and intuitive syntax based on XML specification, which consists of the following two elements: (i)Storage Definition, covering representation of register files and memory systems (ii)Instruction Definition, includes instruction format, category, operation and so on. Besides heterogenous architecture support, the features of Smart-ISDL include support for multiple memory system, variable length instruction and data and register alias. This thesis also discusses in detail about the design and implementation of a code generator that produces ANSI C++ codes with Smart-ISDL input.The major contribution of this thesis is to ease the development of instruction set simulator with high-level abstraction of processor. Such high level models also enhance the maintainability and flexibility of generated simulator as a result.