Research On Instruction Management And System Virtualized Simulation Technique Of Stream Architecture

Driven by the rapid development of VLSI technology and the flowering of the computation intensity applications, high performance scalable parallel computer architecture has been a hot issue in both academic and industrial fields. Stream Architecture becomes an important research direction due to its simple hardware structure, high utilization of the hardware resource, powerful computation ability and high scalability. Stream processors such as Imagine, Merrimac, FT64, MASA, Cell, NVIDIA G80, Storm DSP, Tiles64 and so on have been widely studied. However, as stream architecture being further studied, it's confronted with more and more challenges, for example, low utilization of the on-chip instruction memory, the restriction on the applications caused by the single SIMD execution mode, the contradiction between the cost and speed of the scalable stream architecture simulation. To solve the above problems, this article focuses on the instruction management and system virtualized simulation technique of stream architecture.The thesis has conducted a systematic study on the stream architecture, including kernel instruction codes analysis, on-chip instruction memory design, execution mode in stream architecture, FPGA-based simulation system optimization for stream architecture and so on. The thesis has completed the following main contributions and innovations:1. We present a method to improve the utilization of the on-chip instruction memory, which constructs the instruction memory based on kernel hot code management. We build a Kernel-SPM mode to analyze the hot spot of kernels in stream programs. By analyzing the features of Kernel, we define Kernel Hot Code, and propose a methodology for finding Kernel Hot Code in the kernels of different structures. In accordance with this method, we develop an instruction memory managed strategy which manages the kernel hot code and kernel cool hot separately. We build a software-managed on-chip instruction memory and a hybrid on-chip instruction memory, which uses kernel hot code manage strategy. The experiments show that both of them can reduce the area of the on-chip instruction memory efficiently with little performance loss.2. We propose a domain-divided program compression scheme for VLIW and develop a full distributed on-chip instruction memory for stream architecture. We analyze a series of typical stream applications'VLIW to quantify the nop instruction ratio of each VLIW domain. To solve the poor code density problem, we develop a domain-divided program compression scheme, design a full distributed on-chip instruction memory for stream architecture, and put forward the SIMD pipeline execution mode. The experiments show that domain-divided program compression scheme combined with full distributed on-chip instruction memory can efficiently reduce the memory space and bandwidth demand of the instruction code.3. We develop a Multiple-morph technique and design SIMD pipeline morph, MIMD morph and distributed stream register file for stream architecture. We point out the restriction of the stream architecture applications caused by the single SIMD execution mode. And then we propose Multiple-morph stream architecture to solve the polymorphism of the stream by extending the single SIMD execution mode and introducing SIMD pipeline morph and MIMD morph in the stream architecture. We also design a distributed stream register file and program interface for Multiple-morph stream architecture. The experiments show that, Multiple-morph stream architecture is compatible with the execution mode of the typical stream architecture and meet the need of the new stream applications better.4. We put forward a novel system-virtualized simulation technique and design a virtual simulation platform for MASA stream architecture. We propose a system-virtualized simulation model, including a Virtual Arithmetic Page model, a Memory Page Rotate Model and an intra-Cluster Function Configurable Model. We also present a design methodology for constructing virtual simulation system. We build virtual simulation platform for MASA stream architecture. The experiments show that system-virtualized simulation technique can efficiently reduce the need of FPGA resource in the simulation system, and the increment of the simulation time is acceptable. In addition, we extend the system-virtualized simulation model and further present a Multi-Clock Coupling Simulation Technology for SIMD architecture and a virtual simulation model for SMP architecture. The experiments show that system-virtualized simulation technique is not only suitable for stream architecture, but also efficient in cutting down the resource consumption of the simulation system for Symmetrical architecture such as SIMD, SMP and so on.