Chaotic Encryption Chip Based On Fpga Technology Research

Due to the exceptional properties of chaos such as the sensitivity to initial conditions and parameters, the pseudo-randomness and the ergodicity, chaos-based algorithms have shown their superior performance, especially in swiftly shuffling and diffusing data, which quite superior to traditional schemes of cryptology. However, most currently existing chaotic ciphers are intend to be implemented in software, by which the data are processed sequentially and the throughput is limited, thereby are not suited to hardware realization.In this thesis, two chaos-based parallel cipher schemes that accommodate to FPGA (Field Programmable Gate Array) implementation are presented: one belongs to stream cipher, and the other one belongs to block cipher. The proposed stream cipher scheme is inspired from LFSR (Linear Feedback Shift Register) but differs in the feedback mechanism: the later uses a linear feedback function while the former uses a nonlinear chaotic one. In the block cipher scheme, the two-dimensional chaotic cat map is extended to general 3D for designing a faster image encryption scheme. Besides, the diffuse-mechanism is also used in the scheme, thereby significantly increasing the resistance to statistical and differential attacks.Issues concerning VHDL (VHSIC Hardware Description Language) programming, internal function modular description, encryption results and performance analysis of the encryption chip are reported. Simulation results show that the throughput of the stream cipher can reach high up to 61.622MB per second under the circumstance of not taking the communication delay into account.Experimental tests show that the attempt of applying the two chaotic encryption schemes to hardware implementation is feasible, and can acquire high security and fast encryption speed.