Chaotic Encryption System Research Based On FPGA

With the development of communication technology, computer technology and network technology, network communication has become the main tool to spread information. People can communicate with all kinds of information such as text file and multimedia information which is make up of image and sound through network. So the safety of data information has become more important. How to guarantee the security of information put forwards a higher requirements on Encryption no matter from the encryption algorithm or the system itself. And makes studying how to ensure the security of digital information has become a hot topic.Since E.N.Lorenz discovered the first chaotic attractor in1960s, chaos theory has been obtained huge development and widespread concern in many fields. The excellent performance such as chaos’s extreme sensitivity to initial conditions and system parameter, white noise statistical characteristics and unpredictability make it inherently cryptographic so in recent years the design of encryption systems based on chaotic developed rapidly. While FPGA, the new high density programmable logic devices, has some characteristics such as high integration, agile unit and reprogramming. So it is suitable for design data encryption system. Based on these tips, this paper proposed the design of chaotic encryption system based on FPGA. Based on research of chaotic system and new image encryption algorithm, chaotic encryption system is physically implemented with FPGA.First of all, this paper introduce the basic concept and The development situation of both domestic and abroad of chaos and cryptography, and introduce some typical chaos system. This paper proposed a chaotic cellular neural network system, and in-depth study of the system dynamic characteristics through theoretical analysis and simulation. The analysis results show that the system has a complicated dynamic behavior characteristics. Based on this, the hardware circuit is designed, and the physical implementation of chaos system is completed through the FPGA, and observed all kinds of chaotic attractor to provide pseudo random sequence generator for chaotic encryption System.In addition, based on hyper-chaotic systems have more complex phase-space and dynamic behavior than low dimensional chaotic system, an improved hyper-chaotic AES encryption algorithm which improved the generation method of S box is proposed.To improve the complexity of S box, the method arranged chaotic sequence generated by hyper-chaotic system to form the S box. At the same time, to improve the safety of the algorithm, chaos sequence is used to scramble the location of row and column based on external key.Moreover, according to the design requirements of encryption system, this paper proposed a implementation scheme with FPGA as hardware design platform. This scheme can not only improve the security of the encryption system, and can improve real-time performance of the system. And FPGA has some characteristics such as reprogramming, short design and development cycle, low cost of design and Advanced development tools. So it can update its local resources according requirement to improved flexible of design and reduced costs of development. This paper use VHDL to design bottom module code according unique structure of FPGA and design method of module, and use the method of Schematic to combine bottom module and design top file. Then correctness and functionality of system is verified through simulation and test. Last, project file is completed through compile, pin constraints and so on, then download to FPGA chip to implement chaotic encryption system. Based on this, this paper design human-machine interface with Matlab GUI to finish coordination between PC and FPGA chaotic encryption system.