Developed Spatiotemporal Chaos-based Encryption Chip

Due to the exceptional properties of chaos such as the sensitivity to initial conditions and parameters, mixing, the pseudo-randomness and the ergodicity, chaos-based encryption algorithms have shown their superiority to traditional schemes of cryptology in performance. However, most currently existing chaotic ciphers are intend to be implemented in software rather than in hardware by which the data are processed in series and the throughput is limited, therefore, are not suited to multimedia encryption.Comparing with other chaotic systems, spatio-temporal chaos is of higher dimension, and has more complex dynamic properties. Due to its instinct operational parallelity, spatio-temporal chaos can be used to construct encryption algorithm based on hardware implementation. In this thesis, two schemes based on bi-directional coupled map lattice are presented. One method bipolarizes a chaotic sequence with a threshold to get a binary sequence; the other is based on direct binarization algorithm. Furthermore, the paper analyses the randomness of two schemes and test them with FIPS 140-2 and SP 800-22 issued by National Institute of Standards and Technology (NIST). The test results show that both pseudo-random binary generators (PRBGs) are of good performance.Issues concerning VHDL (VHSIC Hardware Description Language) programming, performance analysis of the encryption chip are reported. Simulation results show that the throughput of the stream cipher can reach high up to 512MB per second under the circumstance of not taking the communication delay into account. Finally the sequences are tested with SP 800-22 and results show that the attempt of applying spatio-temporal chaos to hardware encryption implementation is feasible, and can acquire high security and fast encryption speed.