Design And Implementation Of Decoders For Low-Density Parity-Check Codes

This thesis studies the design and implementation of the soft-decision and hard-decision decoders for Low-Density Parity-Check (LDPC) codes with theoretical analysis and simulation. The main results and contents are as follows.1. The structure and characteristics of Quasi-cyclic (QC) LDPC codes that are propitious to implement are introduced, and an idea to improve the performance of QC-LDPC codes is proposed.2. Three soft-decision decoding algorithms for LDPC codes are introduced, and the one with faster convergence rate and lower memory requirement is chosen for the FPGA implementation of the decoder. An FPGA chip which can provide a throughput of 50M bit/s with 20 decoding iterations has been developed based on Altera Stratix EP1S25 FPGA device. This chip has no performance loss with the use of BPSK modulation on the AWGN channel. A few schemes to reduce power dissipation and logic cell requirement are proposed.3. Bit-flipping (BF) algorithm for hard-decision decoding is discussed. A method to determine the value of threshold is proposed for partially parallel decoding architectures. This method has a higher decoding speed compared with the existing simple BF algorithm. A hard-decision decoder has been developed based on Altera Cyclone EP1C3 FPGA device. The guideline for further reducing memory requirement and improving decoding speed is addressed.4. The Bit-interleaved Coded Modulation (BICM) scheme base on LDPC codes is presented with the use of 8-PSK modulation as an example. The BER performances achieved with various labeling maps of BICM schemes are compared by simulation. Furthermore, the performance of this scheme on frequency-hopping (FH) channels is described and the ability of LDPC codes to combat burst errors is demonstrated by simulation. A scheme to validate the idea of improving the performance of QC-LDPC codes is also presented.