Architecture For Data Stitcher In Reconfigurable Computing Unit

Parallel computing in SoC realized by hardware is an appropriate way to good performance processors, especially to embedded system. But compared to instruction-based processor, hardware-processor loses application flexibility while takes advantage of high computing speed. Reconfigurable Computing (RC) architecture, which is divided into coarse grain and fine grain, supplies a gap of that. To overcome the shortages of both coarse and fine grain RC architectures, a novel RC architecture was proposed.Novel RC architecture based Reconfigurable Computing Unit (RCU) works as a SoC IP, affording computing-intensive applications mainly of encryption and DSP. In RCU, Reconfigurable Cells Array (RCA) burdens computing tasks. Installed around that, Data Stitcher (DS) is RCA's local controller, and DSes are managed by DCC (Data Computing Controller in RCU).Data storage, addressing and communicating with RCA are main responsibilities of DS. Distributed DSes containing data memories shorten the physical path of data accessing and also promote the parallelism of that. Address Generator (AG) in DS closed to data memory is convenient to control data I/O with RCA and supports usual addressing models with high performance. Parameterized Video Addressing Model based AG takes on application expansion as well. Otherwise, synchronous DS communicates with asynchronous RCA perfectly with special I/O ports. The design thought of DS emphasizes standard and modular methods, which offer independence, universal and extensibility.According to verification with the DS prototype in Verilog function descriptions, the validity of our design was proved. This design exhibitions the fundamental of trade-off between performance and flexibility, and supports RCA high speed computing efficiently. With DS, the RCU can work as a whole.