The Design Of Multi-stage Filter ASIC Based On Image Processing

A multi-stage filter based on Gauss pyramid is designed in the paper. It employing different-stage FIR filters can eliminate background, restrain noise, enhance objective. The filter uses 1×3 filtering template with core coefficient 1 and works stably under 50Mhz.It accepts16 bits grey image data and supports 128X128,256X256,320X240 three frame format image data with line scan. Filter's output includes three filtered results and one original image.output data with IDT RAPIDWRITE mode is based on standard dual port interface protocol. Written address is controlled by external programming.First of all, the basic theory of multi-stage filtering algorithm and Gauss pyramid are introduced in the paper. Then the actual design strategy for mapping the algorithm to circuit is analyzed and considered: implementing subsample and reinterpolate operation with multi-frequency; adding zero operation based on the image edge processing; pipelined operating mode; system programmable operation; input filtering coefficient approximately valued; shifter and adder instead of multiplier; employing four caches with 64bits data width on system; image data inputted in slower speed and outputted in faster speed. In the paper, system architecture of the multi-stage filter is partitioned to five modules: data path module,control module,multiplexer,fifo,clock generator according to the designate requirements. All modules are designed in standard RTL description and logically simulated. Finally, the design is through synthesis with CCWSR compile strategy and time verification /analysis. The timing report and back-end waveform show the design's meeting designate specifications and real-time image processing requirements.