Research On Key Technology Of Multi - Core Processor Mapping

With the continuing development of semiconductor technology, more and more transistors are integrated onto one chip. However, the decreasing of feature sizes do not lead to the increasing of frequency of circuits, since the increase of power and reliability problems caused by higher frequency become key problems which restrict the increase of the frequency. Obviously, traditional single core processor cannot improve its performance through the increasing of frequency. Besides, considering about the design complexity and other problems, this architecture has reached its bottleneck. Therefore, multi-core architecture is adopted to continuingly enhance performance of one chip without further frequency increase. And currently, Network-on-Chip (NoC), which was proposed to solve problems of traditional bus-based interconnection in performance, power and scalable, is widely used in inter-core connection of multi-core architecture. Under these backgrounds, this thesis addresses problems of task scheduling and processor core mapping based on NoC based multi-core processor design. Moreover, considering about the widespread use and special feature, pipeline technique is adopted in this thesis.Specifically, a preliminary work of task scheduling and core mapping, namely program feature extraction, is introduced. In this section, SUIF2is applied to extract two groups of data essential in parallel processing, for loop and statement information. Also, instances are given to illustrate the function of the information extraction program.Then, mathematical modeling of the task scheduling and core mapping problem is introduced involves software application, hardware parameter, problem solution and solution objective. In addition, after analysis and discussion, a group of constraints is adopted. And according to feature of the problem, three solution vectors are discussed and transformed respectively, making the decrease of size of the solution space in some extent. As the transformed solution space is a convex polyhedron on the geometric meaning, this model is called convex polyhedron model in this thesis.In the following section, several algorithms of the problem are introduced, and simulated annealing algorithm is adopted in this thesis after analysis and comparison. Then, the algorithm is optimized based on the features of the algorithm and the model, as well as the parameter setting of the algorithm.Lastly, random task graphs and a real application are adopted as benchmarks to test features and effect of the algorithm. A recently proposed algorithm is adopted as a contrast. Experiment results show that the algorithm proposed in this thesis can get2.76～4.63times throughput increase compared with this algorithm in random task graph test, and can achieve at most35%lower energy consumption with the problem scale increase. For the real application test, the algorithm proposed in this thesis can get effective scheme close to artificial scheduling and mapping.