MPEG-4 ASP Video Decoder System Design

Internet is coming into our life more and more deeply, it's content has changed from "text" to "multimedia", today, streaming multimedia become a new application and has a bright future. Though wide-band has been used widely, it's not wide enough to watch high-quality real-time video. Futhermore, wiless communicaton has become a hot technology, it has limited band and unstable communication channel which result in high percentage of errorness In this situation, if people want to watch realtime video, it has high demand that video producer compress the video as small as possible when quality is good enough and receiver have ability of error resilience. MPEG-4 Advanced Simple Profile is presented for application upward, design of it's decoding system is studied in this text.Calculation of MPEG-4 ASP's decoding algorthim is very big because of it's complexity tool (ex. Quarter-Pel motion compensation etc.) , so functional module of decoder should work parallely for realtime decoding. After fully estimating the calculation of every functional module, module's partition is given. Futhermore, control strategy of centralized-control was adopted, each module is connected together with a two-port ram.On the base of Software/Hardware co-simulation, the strategy of local simulation with MAL (multi-abstract layer) is presented. In order to achieve high efficiency of system simulation, the characteristic of data-driven unit are analyzed. The dimension of test vector for data-driven unit could be reduced. Thus, a unit simulation bench is built up. It could access target hardware through SHI (software hardware interface). It provides several interface for each processing unit, therefore, the both local and global simulation could be take place on this simulation bench.By now, the speed of logic computation in processing units is very high with general CMOS technics. However, the speed of the storage memory and the data transform between memory and processing units is not as high as the processing units. It becomes the bottlenneck of the system. With the evolution of the video & image compressing algorithms, the structure of data is more complex and more correlative with each other. In this paper, data storage structure and data bus schedule in SoC are researched to resolved those prominent problems.