| With the development of information technology, people need to solve increasingly complex problems, the traditional serial programming method has been unable to meet the needs of many applications, so parallel computers and parallel programming came into being. At present, a common phenomenon of parallel computer system is that the theoretical peak speed of the computer can be very high, but in the practical application of the effective speed is lower. Under normal circumstances, communication delay, decoding delay and Cache delay is affecting the speed of the main factors for parallel computer, but in most practical applications, parallel computer industry has been recognized as the conclusion is:one of the delays are usually accounted for Cache about 70% of the entire delay. Topics focus on issues surrounding the utilization of cache design method for parallel program conducted in-depth study.The paper introduced the concept of data decomposition and loop-carried dependence etc., and presented an approximately relational model between cache using ratio and the parallel computer effective speed. In order to achieve a purpose that to excavate the instruction-level parallelism as many as possible in the program and to enhance cache using ratio, namely effective speed of parallel system, the paper recounted also a method that how to split and reduce the degree of the data dependence in whole computing objects, by above-mentioned model and an instance.Experiments show that the proposed method in different architectures of parallel platform utilization can reach about 45%, breaking the traditional parallel machine utilization rate of only 25% of the phenomenon. The topic of research results, in order to explore how to combine the hardware features of parallel systems, to improve the parallel programming method, to allow users to apply in the conduct of how the actual performance as close to a peak performance of parallel systems provide a viable approach. |
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