Hardware Design & Implementation Of Common Processing Platform In CMT

The third generation mobile communication system has gained much attention in many countries. In order to meet the needs of development of Chinese mobile communication, NDSC began the project on CDMA technology which is called CMT (Composite Mobile Telecommunication) two years ago. The CMT system has a characterized new architecture based on IP network in which all the sub-systems are connected through IP protocol.The CMT system is made up of eight sub-systems: WAS, CS, LR, PDSN, OMC, WAU, CMG and CSG. If different hardware platforms were used, the complexity of the whole system will increase greatly, so does the maintenance difficulty. Having made a synthetic consideration of systematic architecture character, we decide to design a common hardware platform in order to decrease the hardware complexity and improve the system stability. The platform can be used in some different sub-systems (such as WAS, CS, LR, PDSN, OMC, etc.) with their own software running on it.In the design of the common hardware platform, we taked into account the priority of the PCI bus technology and the PMC techonology, and established the following design principle: the platform is based on PCI bus framework, PrPMC is used as processor and devices complied with PCI Specification are choosed to provide the required functions.According to the function requirements at system level and at board level, the common processing platform is divided into following function module: processor, Ethernet module, bridging module, IDE control module, logic control module and power supply module .In addition, the bridging module is a critical part in the platform. With the two different kinds of implementation methods of bridging function: using specific integrated circuit or using FPGA, the plan of design is finished with two stages. Stage one: with specific integrated circuit to realize bridging function, the design and realization of the platform is divided into five parts according to function, thus the feasibility of the implementation of the platform and rationality of design philosophy are proven. Stage two: using FPGA design to realize bridging function, especially, through replacing the bridge module on the platform realized at stage one, Finally finishing the hardware design and realization of the common processing in system. In the design, the mechanism of distributed power sources is applied to the power module in stage one, providing a highly reliable power supplying solution to board, which implements hot swap ,slow power supply and automatically cutting off etc. thus to improve the stability of the power system.The difficulty of common processing platform lies in in stage two : the design of IP core - -PCI-Local bus bridge,.This thesis analyses the structure and operation principle of this bridge at first, then according to the structure of the bridging module ,fmishes the design of FPGA withfour modules which fulfill the bridging function of IP core - PCI-Local Bus , and succeeds in matching at Spartanll series device X2S50-FQ256-5, Company of Xilinx, finally simulates emulation of bridge of PCI-Local BUS in terms of system level, and detaily analyses the output waveform. Especially, the idea of constructing cycle FIFO in the design of reading/writing of IP core is put forward and implemented; In the design of PCI bus arbitration mechanism, in order to overcome the regular PRI algorithm" full and hungry uneven drawback", A PCI arbitrate algorithm based on rotational PRI is proposed and implemented which can support six PCI devices's bus arbitration.The implementation of stage one has been extensively applied to CMT system at present, which fully proved the feasibility and flexibility of the common processing platform. The critical part - implementation of FPGA of Stage 2 design has already been finished as well as the simulation done.