Design And Implementation Of Mixed-signal Synapse And Neuron Circuits

Artificial neural networks(ANNs)have a wide range of applications in the field of speech recognition,image processing,and automatic control.Originally,ANNs are implemented by software running on computers.When the networks become more and more complex,software simulations cannot provide the computational power required.So the dedicated hardware implementation of ANNs has aroused great concern.As synapse and neuron are the elementary parts to offer the weight storage and operation characteristic in neural networks,designing excellent synapse and neuron circuits is the first step to build the entire neural network.Based on the McCulloch-Pitts model,a synapse circuit and a neuron circuit both with mixed signal are proposed.The mixed-signal implementation can simultaneously have the high precision of digital circuits and the low power consumption of analog circuits,so it is the ideal way to implement neural networks.The synapse circuit stores the weights in MOS(Metal-Oxide-Semiconductor)capacitors and MOM(Metal-Oxide-Metal)capacitors in the form of charge.The variability of the MOS capacitor is used to generate charge redistribution to produce an output.The whole process is in the charge domain without quiescent current,so the power consumption is low.Using the SMIC 1P6M 180 nm CMOS process,the synapse circuit was tape out and the core area is 0.041 mm2.The test results show that the power consumption of the synapse circuit is 0.128 mW and the nonlinearity error is 2.97%at the supply voltage of 1.2 V and the operation frequency of 50 MHz.In addition,using the designed synapse circuit,this dissertation also designed a pure digital input and output neuron circuit,which includes a 2'2 synapse array,charge-sharing SAR(Successive Approximation Register)ADC(Analog-to-Digital Converter),ReLU(Rectified Linear Unit)activation function circuit,resistor string DAC(Digital-to-Analog Converter),some multiplexers and buffers.The synapse array is respon-sible for the multiply-accumulate operation.The ADC is responsible for converting the analog charge into a digital output.The activation function circuit is responsible for implementing the corresponding activation function.The DAC is responsible for converting the digital weight into an analog voltage for synapse array.The proposed neuron circuit whose core area is 0.3429 mm2 was fabricated with SMIC 1P6M 180 nm CMOS process.The test results show that the neuron circuit successfully implements the multiply-accumulate function at the supply voltage of 1.2 V and the operation fre-quency of 5 MHz.The nonlinear error of the multiplication output is 2.67%and the overall power consumption is 0.509 mW.