Based Dual-CPU Chip DECT Protocol Software Design

With the rapid development of telecommunication techniques and the public's improving requirement of communication service, personal communication network has become a very important branch in the field of telecommunication among which cordless telecommunication is exceedingly noticeable. DECT is a kind of digital cordless telecommunication technique that was developed by ETSI in 1992 and was brought to the standard by ITU-R on Nov 5, 1999. Compared with the other digital cordless telecommunication technique PHS and PACS, DECT has the character of high code velocity and flexible frame structure. Compared with GSM, it has the character of high capacity, simple technique, flexible application, low cost, foreground optimism development, and can constitute with GSM with each other network that repair, enlargement capacity of GSM at population density high district.DECT is an access technique that corresponds to the lower 3 layers of the OSI model, and has no agreement at physics construction and application layer in protocol, so a designer should design according to the customer's demand. This paper design the software which meet the voice need for special chip on the basis of analysis protocol. SC14404 is a chip optimized to DECT handsets which is designed by US ns corp., and it has two CPU, co-processor is designed to deal with air data which can realize multi-timeslot format flexibly, select communication speed according to the customer's different need and bring convenience for the future upgrade. This also brings complexity; designer should plan to make out receive and transmit air data, and should notice time orientation accordingly. This paper mainly designs DECT handset's software including resource management which system required, protocol implementation of MAC layer and co-processor communication with main CPU. Resource management consists of task, memory and timer management. While MAC layer is designed to a finite state machine. This paper describes data structure, state transfer chart and some important processes including synchronization, link build, receiving and transmitting high layer traffic data. Lastly this paper explains asm code in DIP level and special design due to memory capacity restriction including interrupt technique.