| Video & image processing is widely used in those fields: digital TV,videoconferencing, digital libraries, distant learning, telemedicine, interactive games.And it places very high demands on devices for transmission, storage, andcomputation.The main object of this dissertation focuses on some bottleneck problems ofmultimedia real-time system: computational speed, data storage structure and data busschedule. Based on video codec, algorithm optimization and integrate circuit designmethodology, this paper gives some proposals to resolve these problems fromdifferent levels.Computational speed is one of the bottleneck problems of multimedia real-timesystem. In this article, fast algorithms for modules of high computational complexityand Intel acceleration instruction sets are deeply studied.There are two kinds of architecture for video & image processing system:programmed and dedicated. The former is more flexible and easy to update. But thehardware is complicated, and power consumption is high. The later is designed andoptimized against a set of algorithms. It saves more hardware and has higherprocessing speed. Actual system often adopts mixed architecture design methodincluding both dedicated and programmed processors. Acceleration methods of themare deeply studied in this article.By now, the speed of logic computation in processing units is very high with generalCMOS techniques. However, the speed of the storage memory and the data transformbetween memory and processing units is not as high as the processing units. Itbecomes the bottleneck of the system. In this paper, data storage structure and databus schedule are researched.Firstly, two kinds of data storage structure are studied: local memory and framememory. The structure in the future is forwarded. Secondly, the bus data schedule isstudied based on the sotrage structure. In video & image processing, the data arecontinuous, periodical and correlative. According to the characters, an AMBA bussystem and a hybrid scheme are developed.
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