Design For One Of The COMS Memory-Pixel Machine

The objective of this paper is the hardware design for one of the CMOS memory. It is used into the VLSI for real-time alternant 3D-shadow picture and colour picture .In the plane of pixel design, the conception that offering the special hardware circuit for every pixel is brought into play ultimatally. So, it can calculate 218-220 pixels at the same time. Because the calculation is divided, each pixel needs very small circuit. Acount for the combination of these circuits and the flame buffer, it has the same area as the present-day memory. Based on the careful analysis of the system 's internal structure, the system is divided into several functional units.Integrally,the system has multiplication ,ALU .memory ,output and control for scan etc.While these bigger units also include some minor functional modules, for instance, the multiplication comprises serial- collateral multiplication module and binary tree multiplication. The design method for the system is top-down method, that means the system is divided into some small function modules on the top level .this division of the system 's function and hierarchy will reduce the complexity of design work and is convenient for the designers to find out the bugs earlier. After the system-level spec and the division of the design hierarchy are comfimed,we start to design the digital logic circuit from the bottom for the pixel machine .VHDL is used to describe the digital logic .the behavioral description of the digital logic circuit is made in VHDL at first, then this description is functionally simulated by the logic simulation software. If the description is corret,the design flow will continue. The interconnecting of the modules on the same design level comprises the hardware structure of this level and the simulation can be made on every level of the design. After all the modules are completed and tested, they can be connected together from the bottom and form the whole system-level design.