Soft Core Design Of Parallel Port And Cache Of Video DSP

this paper is based on national 863 project " soft core design of video DSP" . This paper studies the structure of parallel processing computer , and design the soft core ofXY-VDSP.First ,we bring forward the system design of XYDSP based on analyze of parallel processing computer. XY-VDSP adopt the SEMD array processing computer structure ,and the Harvard Bus is using in the bus structure.The important of parallel port and cache is introduce in the paper. The design is narrated in detail include the interface signal ,module depart, control state machine.XY-VDSPIS designed with Verilog Hardware Description Language. We use Altera FPGA APEX II20KE 1000K to implement our design.