| This thesis has given out a detailed introduction on the Research&Development of the Digital Multiplexer which is used in the power line as a part of the DPLC (Digital Power Line Carrier). In addition, this article has analysed the necessity and feasibility of the research. Meanwhile, as a major work of this thesis, it emphasized on the frame structure design, the timing analysis and the solution of modem block unit. The Digital Multiplexer applied all sorts of advanced DSP (Digital Signal Processing) technics, including voice compressing technic, multidimension modulation/demodulation technic and TDM(Time Dividing Multiplex) technic etc. The whole equipment is composed of six functional blocks unit, they are voice compressing unit, synchronization/asynchronization data converting unit, manage unit, clock unit, modulation/demodulation unit, and multiplex/demultiplex unit. By the design of the frame structure, the digital multiplexer can accomplish four kinds of multiplex plans to adapt different channel condition. Voice compressing applied the technic of MBE(Multi-Band Excitation) with the data compressing speed is 4.8kb/s. The data output from modulation/demodulation unit is modulated by means of TCM(Trellis Code Modulation) technic and demodulated in Viterbi tchnic. In the actual circuit, the CPU of voice unit, data unit, multiplex/demultiplex units are all ATMEL89c52 chip. The program of voice unit, data unit, multiplex/demutiplex unit are programmed in assemble language. The hardware circuit has been debugged and running in real time, the result is satisfied.
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