Research And Development Of An FPGA Based Control System For High Speed Line Scan CCD Camera

With the development of machine vision technology, line scan CCD camera has been widely used in presswork monitoring and detecting areas. However, the nonuniformity of the velocity of the presswork always results in nonuniformity of sampling rate, which may lead to distortion of the image. Therefore, in this paper a kind of line scan CCD sampling rate control system based on FPGA is presented, in order to improve nonuniformity of sampling rate.First of all, the architecture of the whole system is analyzed. The architecture of the system is based on the form of MCU+FPGA. The FPGA realizes the digital processing of optical encoder signals, while the MCU transfer relevant information from the FPGA to PC by its serial port.Secondly, median filter algorithm is selected as the filtering method according to the nature of noise of the encoder signal, and the architecture of its implementation on VLSI is discussed in detail. Then the structure of the whole control system implemented on FPGA is presented, as well as the Verilog HDL code of the system and the implementation results of the system by the ISE software.The schematic and PCB of the FPGA child board is also presented. After introducing the type of FPGA employed in this paper and the schematic of the child board, the PCB of the FPGA child board is designed from the perspective of interference prevention, focusing on the power distribution system, crosstalk between signal traces and signal reflection along traces, to improve the electromagnetic compatibility of the system, which is critical to the stability of the whole system.After the above research, this article presents the schematic and PCB design of the MCU motherboard as well as the MCU software design. The MCU motherboard provides signal interface and drive, which transform the encoder signal to FPGA compatible signal and transfer the CCD drive signal to CCD camera. Meanwhile, MCU transfer relevant information from FPGA to PC, which provides relevant information for the PC software compensation.Finally, experiments are made to test the performance of the system. The experiments results are analyzed to verify the design.