Research On Controller Level Life Extension Technologies Of Flash Memory Devices

NAND Flash-based solid state storage devices are widely used in mobile devices,desktop computers,data centers,and high-performance computing systems.The repeated charging and discharging of cells lead to gradual wear of the insulating oxide layer in the cells,resulting in serious lifetime problems.To improve the lifetime of solid state storage devices,this dissertation proposes dedicated optimization schemes via reducing the damage induced by data written and increasing bit error tolerance rates from three dimensions of controller: cell-level data representation,garbage collection,and hierarchical error corrections.The effectiveness and efficiency of those schemes are evaluated and verified by modeling,simulation and prototyping-based experiments.The main research contents and contributions of the dissertation include:To address the problem that the higher the voltage is,the greater the wear of the flash cell is,based on the phenomenon that the damage induced by charging and discharging the memory cells is exponentially increasing with cell electric potentials,a novel data representation method,named combination codes,is proposed to eliminate or reduce the probability of high voltage and reduce the wear when storing data.More specifically,the key idea of combination codes is to use as more low voltage combinations across cells to represent data as possible,so as to effectively reduce the usage of high electric potentials under the condition that data can be compressed and/or Out-Of-Band(OOB)can be fully utilized.The mathematical analysis results show that,compared to the traditional method,combination codes can reduce the damage by 55.89% in MLC,where the damage contributed by the bit data ‘01’,which is represented by the highest electric potential,is reduced by 62.29%.In addition,an access pattern aware data layout is proposed to reduce the read amplification induced by combination codes.The experimental results show that with access pattern aware data layout,the damage can be reduced by 9.89% to 42.74%.To address the problem of write amplification caused by mixed storage of hot and cold data,based on the phenomenon that most of the valid data to be migrated during garbage collection is infrequently updated(i.e.,cold data),a novel method of separating cold and hot data through garbage collection,named Isolation,is proposed to eliminate or reduce write amplification.Dedicated active blocks are designed to store GC-written data and contruct cold data blocks.In such a manner,GC-written data is isolated from other written data,and thus effectively reducing the overhead of frequently moving the cold data during garbage collections.Moreover,Isolation can be integrated into other hot data oriented hot-cold data separation methods.Experimental results based on simulation show that Isolation can reduce the number of erasures by 47.3% and the average I/O response time by 80.1%.And Isolation can further reduce the average I/O response time by 7.8% to18.5%,and the average I/O response time by 10.7% to 41.4%,when it cooperates with other hot data oriented hot-cold data separation methods.To address the problem of insufficient error correction capacity and long decoding latency of existing in-page error correction codes in solid state drives(SSDs),based on the phenomenon that original data can be reconstructed by data redundancy,a novel heterogeneous two-layer error correction method is proposed.Specifically,the core idea of this method is to store user data on MLCs and to store verification redundant data on SLC.By adding a small capacity SLC chip to store redundant data generated from cross-chip data,those redundant data can be used to correct the bit errors which cannot be corrected by in-page error correction codes.Because SLC chips have faster read,program and erase performance,cross-chip redundancy has little impact on the overall I/O performance.Therefore,this method not only achieves the purpose of improving the tolerance of flash bit error,but also solves the bottlenecks of performance and wear.Results collected from both modeling and simulation experiments show that the lifetime of SSDs is increased by23% to 178% via using the heterogeneous two-layer error correction method,compared to traditional in-page error correction methods.