The Research On Acceleration Technology Of FPGA Programmable Network Interface Card For Data Center

In recent years,the emerging application scenarios such as machine learning,distributed computing and Internet of Things put forward higher requirements on the scale and computing power of the data center.The slowdown of Moore’s Low and the invalidation of Dennard’s Low make it more difficult to improve the computing capability of the CPU without increasing the power consumption significantly.Therefore,the CPU needs to allocate more time for network-related processing rather than upper-level applications.In order to close this ”performance gap”,academia and the industry aim to accelerate infrastructure services and tenant tasks via heterogeneous computing platforms such as FPGAs and GPUs.Among them,the FPGA programmable NIC has attracted the attention of researchers due to its good tradeoff on programmability and energy consumption ratio and its key position that ”bridging” the servers and data center networks.To tackle the challenges such as programming complexity,precise tenant isolation and high application data conversion overhead,the thesis proposed an acceleration framework for FPGA programmable NIC and a set of key technologies to accelerate the main tasks on the network layer,transport layer and presentation layer on the NIC.The main contributions include:(1)To reduce the difficulty of programming the FPGA programmable NIC and the complexity of software and hardware co-design,an FPGA-oriented software and hardware co-design framework is proposed.The framework is based on a custom module ID index mechanism and metadata to support flexible pipeline configuration.It hides the details of the FPGA and hardware/software interfaces from users through a unified interface.Therefore,the development and deployment of different functions for FPGA programmable NIC can be greatly simplified at the network layer,transport layer,and presentation layer.(2)At the network layer,in order to support the programmable and high-performance processing of the virtual network functions of the end system,and to realize the function and performance isolation of the multi-tenant virtual network at the same time,a highperformance programmable network forwarding model with tenant isolation is proposed and implemented.Based on the high-performance programmable basis provided by RMT,this model uses virtualization mechanisms such as page tables to achieve inter-tenant isolation.Experiments based on FPGA programmable NIC prove that this forwarding model can realize tenant-isolated high-performance programmable forwarding in a 100 Gbps data center scenario.(3)At the transport layer,in-depth performance testing and analysis of the QUIC protocol,which is an alternative protocol to the TCP protocol,has been conducted in a variety of network scenarios.Thus,the key performance bottlenecks in the QUIC protocol are located.In addition,according to the located performance bottleneck,a QUIC protocol offloading mechanism based on FPGA programmable NIC is proposed,which reduces CPU overhead and improves QUIC protocol processing performance through partial offloading.(4)At the presentation layer,in view of the problem of ”data center tax” occupying more CPU overhead,a presentation layer offloading mechanism based on FPGA programmable NIC is proposed.This mechanism offloads the ”presentation layer” operations including encryption and decryption,compression and decompression,and vectorization of the text,and further releases the computing power of the CPU to upper-layer applications.In addition,the FPGA prototype system experiment proved the feasibility and scalability of the proposed mechanism.The thesis used the real-world FPGA programmable NIC to evaluate the proposed prototype system in detail in terms of function,performance and resource overhead,fully verified the advantages and feasibility of the technologies proposed above.