Key Technology Research Of High-performance Programmable Logic Controller Based On FPGA

With the growing application of programmable logic controller, PLC software scale expansion led to extend the scan cycle, so that the PLC can not meet the strict requirements of real-time response time needs of the industrial control system. At present, the international academic research is still in its initial state to build a high-speed programmable logic controller, the mature PLC architecture system implementations has not yet formed. Useful exploration of key technologies to build a high-performance PLC and proposed a number of possible ways, has a certain significance for the development of high-speed programmable controller in this work.The work of this paper mainly includes the following aspects:(1) Put forward the overall implementation scheme of programmable logic controller based on FPGA.(2)Put forward the verification method that proposes the ladder diagram topology structure to be correct.(3) Establish the binary decomposition tree BDT model, which can be used as the intermediate representation that conform to the IEC61131-3standard ladder diagram.(4) Put forward the automatic generation algorithm of VHDL code, such as the ladder diagram Boolean logic, function block, timer, counter and etc.(5) Put forward the analysis method of ladder diagram data dependence, establish the BDT data dependence model, and support the concurrent execution of ladder diagram program on FPGA.In order to test the functionality and performance of the FPGA PLC, the author designed the experiment controlling the traffic lights.and the experiment of the performance compared with the traditional PLC in the EDA/SOPC GW48-PK3experimental development level.