Silicon Based Wideband Microwave/Millimeter-Wave Phased-Array Integrated Circuit

With the increasing demand of 5G wireless communication,"electronic information plus",smart city,unmanned driving and other applications,high-performance,highly integrated,and low-cost silicon-based transceiver system becomes the core component of wireless systems.Among them,the integrated wideband phased array transceiver system works in millimeter and submillimeter bands,which have the capability to support high data-rate transmission,has been paid more and more attention by the researchers at home and abroad because of its wide application prospect in large data rate wireless system.To adapt the complex application environment of future wireless communication systems,communication devices should not only work in various frequencies,bandwidths,and working modes,but also adjust their operating status intelligently based on actual application scenarios to meet the performance requirements of various applications.Therefore,in this doctoral dissertation,the high data rate broadband intelligent phased array transceiver system and sub-circuit are studied,while the theory and design procedure of dual-path noise-cancelling,reflectionless receiver,reconfigurable phase-and gain-control phased-array,time division modulation phased-array transceiver,and the link tracking phased-array transceiver are presented.Multiple chips are designed and fabricated based on CMOS technique,including the integrated 23-40GHZ phased array transceiver.The main contributions of this dissertation are summarized as follows:1.Dual-path noise-cancelling LNA.To solve the design problem of millimeter wave broadband noise-cancelling low noise amplifier,the noise characteristics of transistors in millimeter wave circuit are studied.A dual-path noise-cancelling low noise amplifier is proposed,the design flexibility and noise-cancelling performance are improved by combining amplitude adjusting amplifier.Meanwhile,a three-coil coupling transformer is utilized,which can introduce a g_m-boosting operation and provide a wideband interstage matching.Based on the reconfigurable phase tuning line with high quality factor,a phase compensation circuit is proposed to compensate the effect of process deviation on noise cancellation performance.Based on the structure mentioned above,a22.9-38.2GHZ low noise amplifier is implemented and fabricated using 28-nm CMOS technique,the measurement exhibits a minimal 2.65d B noise figure.2.Reflectionless receiver.To solve the problem of interference caused by high-order mixing products and intermodulation,the architecture of reflectionless receiver is developed.By using an absorptive IF amplifier to eliminate the out-of-band interference signal reflected to the mixer,the high-order mixing products are significantly reduced.The absorptive IF amplifier is designed based on a novel compact on-chip signal absorption network,which can be easily integrated compared to the conventional bulky absorption network.Based on the aforementioned mechanism,a reflectionless receiver is implemented and fabricated using 28-nm CMOS technique.The proposed receiver can support 1024-QAM,1.5Gb/s and 256-QAM,3.6Gb/s data-rate within the operation frequency range of 22.6-39.2GHZ.3.Reconfigurable phase-and gain-control phased-array receiver with high image-rejection ratio.To achieve high dynamic range and high phase-tuning resolution in low power broadband phased-array system,the phased-array receiver with reconfigurable phase-and gain-control is presented.The maximum 14-bit phase-and gain-control is introduced without increasing power consumption by configuring the RF and IF circuits,respectively.The 10-bit maximum effective phase resolution and gain control range>35d B are achieved.Meanwhile,the dual-mode 28-52d B high image-rejection ratio is achieved within the operation frequency range of 23-40GHZ by reconstructing the digital control code without using external circuit module.Based on 40-nm CMOS technique,a four-channel phased-array receiver is implemented and fabricated,which can support 256-QAM,2.4Gb/s and 64-QAM,3Gb/s data rate.4.Time division modulation transceiver.The digital transmitter can improve the efficiency of wireless system,but the digital transmitter is difficult to be integrated in the conventional transceiver architecture,which limits the application of the digital transmitter in the phased-array transceiver system.By introducing the time division modulation mechanism into the local oscillator system,the digital direct modulation module of the digital transmitter can be reconfigured in receiving and transmitting mode.In the transmitting mode,the time division modulator is operated as direct modulator to convert the baseband signal into radio frequency,while in the receiving mode,the time division modulator is worked as local oscillator driver.The time division modulator can improve the system efficiency and LO driving flexibility.An eight-channel phased-array transceiver is implemented and fabricated using 40-nm CMOS technique,which achieves30.4%peak system efficiency in transmitting mode and 5.3 minimal NF in receiving mode within the operation frequency range of 23-40GHZ.Meanwhile,the proposed phased-array transceiver can support 16-QAM,8Gb/s and 64-QAM,4.8Gb/s data-rate.5.Link-tracking phased-array transceiver.To establish point-to-point communication with high-speed moving target,a link tracking technology is developed.The tracking loop in the phased-array receiver automatically identifies the incident direction of the signal and combines with the off-chip decoding system to automatically generate the phase control code of the phased-array transmitter,which can automatically establish a point-to-point transceiver-receiving link with the communication target.The eight-channel phased-array transceiver based on 40-nm CMOS can supportμs level link tracking time.