| High voltage BCD（bipolars-CMOS-DMOS）process makes Bipolar devices,CMOS devices and DMOS power devices on the same chip at the same time.Combining the advantages of each of the three types of devices,it gives designers the flexibility to design power integrated circuits that integrate power,analog and digital signal processing functions.Since the first successful research and development of STMicroelectronics in the 1980s,the high-voltage BCD process has become the mainstream manufacturing process of power integrated circuits in a short time,and has had a profound impact on the field of power semiconductors.From the classification of substrate materials,the BCD technology includes the bulk Silicon technology,the SOI（Silicon on Insulator）technology and the Partial SOI technology.In recent years,with the development of high-voltage BCD technology towards high integration,high reliability and modularity,a series of requirements such as high reliability,high power density and high process compatibility are put forward for its core high-voltage lateral devices.In aerospace and other special fields,it is also necessary to design the high voltage lateral devices in the platform for radiation hardening to meet the application in harsh radiation environment.In this dissertation,a series of studies are carried out to optimize the performance of the new structure,improve the reliability and strengthen the radiation hardening of the core high voltage lateral devices in the high voltage BCD platform,and some achievements have been made.The research content and main innovations are described as follows:1.In view of the influence of total ionizing dose on electrical characteristics in high-voltage SOI LDMOS,the degradation mechanism and radiation hardening technology are studied.The experimental phenomenon that breakdown voltage of high-voltage SOI LDMOS rises first and then decreases with radiation dose is explained,and the degradation mechanism of breakdown voltage under total ionizing dose is revealed.Based on the dielectric field enhancement theory of high voltage SOI LDMOS devices,a device level total ionizing dose hardening technology is proposed.The device level radiation hardening technology is compatible with process radiation hardening technology.By carefully designing the electric field distribution in the initial state of the device,the rising trend of breakdown voltage of the high-voltage SOI LDMOS in the initial stage of total ionizing dose is used to achieve the improvement of the tolerance of the device to total ionizing dose.Furthermore,the traditional total ionizing dose model only considers the charge distribution of the positive oxide trapped charge under positive electric field bias（the direction of the electric field in the oxide is directed to the Si/Si O2interface）,so the total ionizing dose of high-voltage SOI LDMOS cannot be accurately simulated.In order to solve this problem,a model of total ionizing dose induced positive oxide trapped charge under full electric field bias is obtained by designing a back-gate bias experiment.By substituting this model into TCAD simulation and considering the charge saturation effect of positive oxide trapped charge at the Si/Si O2 interface,the degradation curve of high voltage SOI LDMOS with total ionizing dose can be accurately simulated.The simulation results based on this model can provide guidance for the design of total ionizing dose hardening of high voltage SOI LDMOS,and help accelerate the research and development process of radiation-hardened high voltage SOI BCD platform.The experimental results show that the designed 80 V SOI LDMOS has a radiation hardening level of 500 krad（Si）.2.The static characteristics optimization and reliability research of two kinds of core high voltage lateral devices in 700 V BCD platform are carried out.In terms of power LDMOS device,a new structure of Triple RESURF LDMOS with N-P-N layer is proposed,and the analytical model of BV and Ron,sp is obtained through theoretical derivation.In view of the abnormal burning phenomenon in the experiment,combined with the simulation,the failure mechanism of the burning phenomenon caused by hole injection in bird’s beak is revealed.After the reliability optimization,the hole injection probability in bird’s beak of the device decreases by more than three orders of magnitude.The experimental results show that the highly reliable LDMOS structure achieves the characteristics of BV=535 V,Ron,sp=32.38 mΩ·cm2,which meets the expectation of the theoretical model.In terms of high-voltage starting JFET devices,aiming at the shortage of safe operation area caused by space charge modulation effect in traditional high-voltage JFET devices,a high-voltage JFET with lightly doped Sense terminal is proposed.The trade-off between the on-state breakdown voltage and saturation current capability of JFET devices is analyzed.The experimental results show that the structure can achieve the saturation current capacity of 0.125 m A/μm with the on-state breakdown voltage of850 V and the off-state breakdown voltage of 855 V under the drift region length of 91μm,which can meet the approval of 800 V application.Toward not affecting the electrical characteristics of the main power LDMOS device,the variably doped high voltage JFET structure is further proposed and verified by simulation.The results show that the variously doped high voltage JFET can further increase the saturation current by 21.6%compared with high voltage JFET with lightly doped Sense terminal.3.Aiming at the reliability problem of 600 V high-voltage and low-voltage isolation structure and the leakage problem of integrated bootstrap high voltage diode.The 600 V high reliable N-type thin epitaxy Divided RESURF structure was designed.The process window design and reliability performance of two structures were discussed,and the experiment with reliability qualification were completed.A novel high voltage integrated bootstrap device structure with low leakage current is developed,which avoids the leakage problem of traditional diode substrate at the device level.The working mechanism of the bootstrap device under different operating modes is studied.The dynamic characteristics of the bootstrap device including the self-turn-off behavior and the equivalent reverse recovery process are discussed.The experimental results show that the charging current of the proposed high voltage integrated bootstrap device is 11.52 m A and the substrate leakage is 3μA at typical operating voltage.And the device can withstand 970 V at off-state bias.Compared with integrated high-voltage diode,this structure improves bootstrap charging efficiency and reduces the risk of latch-up issue at low-side circuit caused by substrate leakage. |
