Uniform And Ultrathin High-? Gate Dielectrics For Two-dimensional Lowpower Electronic Devices

In the past six decades,silicon-based semiconductor complementary metal-oxide-semiconductor(CMOS)field-effect transistors have developed rapidly in the tendency of continuous shrinking device size and increasing transistor density under the guidance of Moore's Law,making chip computing faster and faster.Mankind fully enjoys the convenience brought by information technology.Today,the latest silicon-based chips have accommodated billions of field-effect transistors,and the size of transistors has shrunk to the nanometer dimension.However,as the size of transistors continues to decrease,problems such as thermal power consumption caused by the short-channel effect have become more and more serious,making the development of the silicon-based integrated circuit industry face many huge challenges.In this regard,the latest International Semiconductor Roadmap(ITRS 2.0)points out that it is necessary to develop new principles,new materials,new device structures or new system architectures to continue Moore's Law.Studies have shown that the reduction of the channel thickness is the basis to ensure the continued shrinking of the device size,and the existence of quantum confinement effect makes the traditional three-dimensional material thickness down to sub-5 nanometers,resulting in a sharp degradation of device mobility.The two-dimensional(2D)semiconductor material has the characteristics of non-zero band gap,limit channel thickness,high mobility,etc.,which can significantly increase the gate control ability,and is one of the most promising new materials to continue to extend Moore's law.However,due to the lack of dangling bonds on the surface of the 2D material,it is difficult to integrate a high-?gate dielectric layer with high interface quality,uniform flatness,ultra-thin thickness and high robustness on its surface using standard atomic layer deposition processes,making the 2D semiconductor-based transistors is facing the problems of high working voltage(V_dd),high power consumption and low yield.Therefore,the development of an ultra-thin gate dielectric layer integration process aimed at the characteristics of 2D materials and meeting the needs of future devices and the realization of low-power 2D transistors are the basis for the application and development of 2D semiconductor material devices in microelectronics.In response to the above-mentioned problems,this paper develops a process for van der Waals to integrate an ultra-thin gate dielectric layer on 2D materials,and studies the dielectric properties of the gate dielectric layer,and fabricates and implements low-power 2D transistors and circuits.This technology breaks through the bottleneck that it is difficult to deposit ultra-thin high-quality oxides on existing 2D materials,and is expected to promote the development of 2D semiconductor materials in the field of large-scale device arrays and integrated circuits.The main research contents are as follows:(1)Integration technology of ultra-thin gate dielectric.This technology uses a single-layer perylenetetracarboxylic dianhydride(PTCDA)molecular crystal film as a buffer layer to achieve the deposition of a high-?hafnium dioxide(Hf O₂)film on 2D material.Among them,the monolayer PTCDA crystal film has an atomic-level thickness(?0.3 nm),and it is coupled with the 2D material substrate by van der Waals interaction,which greatly reduces the effect of the buffer layer to the equivalent oxide thickness(EOT),and ensure that the inherent characteristics of the two-dimensional material are not affected.The oxide film prepared by this technology has the characteristics of ultra-high flatness(RMS?130pm),ultra-thin thickness(<2 nm),etc.,is suitable for a variety of 2D materials,and is compatible with large-area chemical vapor deposition samples.(2)Study on the dielectric properties of ultra-thin gate dielectrics.First,the graphene and Hf O₂ dual-gate transistors were prepared,and the dependence of the thickness of Hf O₂ on EOT and effective dielectric constant was studied.The results of statistics and model fitting of devices with different Hf O₂ thicknesses were obtained.The dielectric constants of monolayer PTCDA film and Hf O₂ are 2 and 15.8respectively.Especially when the thickness of Hf O₂ is reduced to 1.45 nm,the EOT of the ultra-thin gate dielectric reaches 1 nm,which is the result of the smallest EOT of the gate dielectric layer deposited on the 2D material when the paper was published.Secondly,we studied the breakdown characteristics of ultra-thin gate dielectrics.Through breakdown testing and statistical analysis of devices with different thicknesses of Hf O₂,the breakdown voltage is proportional to EOT.Under the same EOT,the breakdown voltage of ultra-thin gate dielectrics is higher than the reported values of other processes.It is worth emphasizing that the leakage current density under 1V voltage reaches the leakage current level of the silicon-based Hf O₂ gate dielectric layer,which is four orders of magnitude lower than the leakage current of the silicon-based Si O₂ gate dielectric layer,and meet the ITRS's performance indicators for low-power devices.Especially when the EOT is 1 nm,the breakdown electric field strength is as high as 16.5 MV/cm,creating the record of the highest breakdown electric field strength of the gate dielectric integrated on 2D material.The corresponding carrier concentration is as high as 6.5×10¹³ cm^-2,much higher than other reported results,reaching the level of ionic liquid gate.Finally,the high-frequency properties of the ultra-thin gate dielectric were studied,and graphene radio frequency transistors with a channel length of 500 nanometers and a gate length of 360 nanometers was prepared.Its cut-off frequency is 10.9 GHz and the intrinsic cut-off frequency is 60 GHz,which is better than other reports.These results indicate that the PTCDA/Hf O₂ composite gate dielectric has excellent dielectric properties.(2)The application of ultra-thin gate dielectric in ultra-low power 2D semiconductor devices and circuits.2D semiconductor CMOS top-gate transistors were prepared,and the subthreshold swing(SS)of the device was reduced to the thermodynamic limit of 60 m V/dec,and the working voltage was reduced to 0.8V.Statistical analysis showed that the device prepared by this process had high uniformity.In addition,short-channel Mo S₂ transistors with a channel length of 20 nm were prepared,with an off-state current of less than 1p A,a switching ratio of up to 7 orders of magnitude,and was completely immune to short-channel effects.Furthermore,using WSe₂ as the P-type channel and Mo S₂ as the N-type channel,a CMOS inverter was prepared,which achieved a gain of up to 12 V/V at supply voltage of 0.5 V,and static power consumption less than 0.8 n W.Finally,a centimeter-level top-gate transistor array was prepared using chemical vapor deposited Hf O₂ thin film samples,achieving a device success rate as high as 90%.The device performance has a high degree of uniformity,which proves that this technology has great potential in the future 2D large-scale integrated circuit field.