| As modern MOS technology evolves, adequate engineering of semiconductor/gate dielectric interface continues to be a critical part of any MOS device development. New device configurations, new gate dielectrics and new substrate materials further complicate technical problem involved. In proposed research, an interface between silicon and gate dielectric is investigated using two different types of MOS capacitors that represent different aspects of evolution of Si/SiO 2 interface.; First, the interface between Si and mist-deposited high-k dielectric thin film is investigated. Effects of process parameters on the re-growth of interfacial layer are considered. It is found that in-situ surface preparation methods, such as native oxide removal with anhydrous HF/methanol and surface passivation with UV/NO as well as increased Hf content in an interfacial layer, result in superior electrical properties of the MOS gate stack. Also, the interfacial layer plays a major role in charge trapping phenomenon during electrical stress on the dielectric layer.; Second, thermally grown SiO2 in U-shaped trenches is tested to investigate the interface between Si sidewall and thermally grown oxide. High quality vertical Si/SiO2 interface is essential to obtain good performance of a UMOSFET in power application and double-gate FinFETs in advanced CMOS technology. Since the vertical sidewall is patterned using reactive ion etching, varied surface preparation methods are considered that include damage control of the surface. Conventional method using sacrificial oxidation followed by wet etching is compared with one-step, gas-phase method that slightly etches Si surface using UV/Cl2 process. Furthermore, possible scaling-down is tested for thinner gate oxides than usual 60nm gate oxide.; In addition to the above, select aspects of SIC surface processing are discussed in the Appendix. |
