Electrothermal Characteristics Of Si-based InP HBT Devices And Circuits

Moore's Law,which has lasted more than half a century,is about to be ended.For the development of integrated circuits in the future,heterogeneous integrated circuits including III-Vs and Si CMOS devices have the characteristics with smaller volume,higher performance,and lower cost.InP HBT devices have many excellent characteristics such as ultra-high frequency and high linearity,making InP HBT/Si CMOS heterogeneous integration technology very promising.In a variety of heterogeneous integration processes,Si-based InP heteroepitaxial growth is the most promising approach to achieve high-quality,high-precision,high-performance,and high-flexibility InP/Si heterogeneous integration.However,because of the different crystal structure and the large lattice mismatch of InP and Si,the first problem is how to grow a high-quality InP epitaxial layer.Moreover,during the Si-based InP heteroepitaxial process,thicker ternary III-V compound buffer layers are usually used to suppress the formation of defects.However,their thermal conductivity is very low,which is very unfavorable for the transistors to dissipate heat to the Si Substrate through the buffer layer.In addition,InP HBT usually works at a higher current density with serious thermal problem,so the heat dissipation of Si-based InP HBT devices and circuits will be very prominent.Therefore,this dissertation will focus on the electrothermal and process problems of the Si-based InP heteroepitaxial technology.The main work and innovations include the following aspects:(1)A novel electrothermal analysis algorithm—SATSM-I(semi-analytic temperature superposition method base on iteration),is proposed to solve the problem of low calculation accuracy of the SATSM(semi-analytic temperature superposition method).The algorithm innovatively proposes the concept of"internal ambient temperature"for the device.Each device in the circuit is given an independent internal ambient temperature.Through continuous iteration of the internal ambient temperature,the changes of thermal conductivity of materials caused by thermal coupling effect of multiple devices are taken into account.Not only can the accuracy of the algorithm be improved,but also the efficiency of the temperature superposition calculation can be maintained.The simulation and experimental results show that compared with the SATSM algorithm,the SATSM-I algorithm can accurately calculate the junction temperature of the devices and greatly reducing the error with high efficiency.This algorithm can be used to calculate the temperature distribution of large integrated circuits with high precision and high efficiency.(2)The influence of different buffer layer structures on the electrothermal characteristics of Si-based InP HBT devices was studied to construct the correlation between the electrothermal characteristics and the epitaxial process design of the devices and provide an optimized design scheme for the Si-based InP buffer layer.The buffer layer structure includes In_xGa_1-xP/Ga P,In_xGa_1-xAs/GaAs,In_xGa_1-xAs/GaAs/Ge/Si O₂,and In_xAl_1-xAs/GaAs/Ge/Si O₂.The results of simulation analysis show that In_xGa_1-xP and In_xGa_1-xAs which have lower thermal conductivity will cause serious heat dissipation problems with thicker thickness.In comparison,the thermal conductivity of In_xAl_1-xAs material is larger,which can alleviate the serious heat dissipation problem,thereby effectively improving the electrothermal characteristics of the device.Compared with the Si-based substrate,the Ge/Si O₂/Si substrate does not significantly deteriorate the electrothermal characteristics of the device,so In_xAl_1-xAs/GaAs/Ge/Si O₂ is a good buffer layer design scheme.(3)The electrical and thermal characteristics of Si-based InP HBT devices and circuits were studied in detail.First,the proposed SATSM-I algorithm was applied to the electrothermal analysis of a Si-based InP HBT frequency divider circuit.The algorithm can calculate the temperature distribution of the circuit quickly and accurately,indicating that the SATSM-I algorithm has good compatibility with heterogeneous integration processes,and its application range can be extended from homogeneous circuits to heterogeneous integrated circuits.Secondly,the influence of temperature change on circuit performance was analyzed.The results show that for larger circuits,small changes in temperature can also have a serious impact on the circuit performance.Therefore,taking into account the electrothermal characteristics,the design solutions for many InP HBT/Si CMOS heterogeneous integrated circuits were provided.(4)Si-based InP heteroepitaxial process and growth mechanism were studied with GSMBE technology.First,a two-step growth method was used to grow InP on the Si substrate directly,and the effect of low-temperature nucleation layer growth temperature on the quality of the InP epitaxial layer was studied in detail.The experimental results show that there is an optimal growth temperature for the low-temperature nucleation layer.At too low or too high temperatures,the crystalline quality of the material is poor.Next,the effect of different growth thickness of the low-temperature nucleation layer was studied.The experimental results show that with the increasing thickness of the growth,the crystal quality of the InP epitaxial layer is better.In addition,the linear graded buffer layer of In_xGa_1-xAs/GaAs and In_xGa_1-xP/Ga P are studied.The experimental results show that with the growth time increase of the linear graded buffer layer,the gradient rate of the material component is slower,so the defect density in the surface InP material is lower and the crystal quality is better.Since the lattice range from Ga P to InP is larger,the gradient rate is faster under the same gradation time,so the crystal quality of the InP layer on the In_xGa_1-xAs/GaAs structure is better.These research in this dissertation have a strong guiding significance for the electrothermal analysis and design of Si-based InP HBT devices and circuits.