Research On Digital Signal Processing And VLSI Implementation Of 3GPP LTE Downlink Receiving System

With the advance of mobile communications, voice service is not the only applications. Driven by services such as mobile internet, vedio phone, streaming media, and mobile TV, mobile communication technology advances towards providing a higher and higher data rates. The Long Term Evolution (LTE) released by the 3rd Generation Partnership Project (3GPP) is one of the most potential mainstream standard for next generation mobile communictions. LTE outperforms its competitors beacause it is of high data-rate, more flexible spectrum utilization, low latency and rich applications.There are some challenges that may slow future application of LTE. One is the power and cost constraints of mobile stations (MS). Compared to its 2G and 3G counterparts, LTE mobile stations are required to do more Digital Signal Processing (DSP) operations in a higher frequency (because the widest bandwidth defined in LTE standard is 20 MHz, and the corresponding sample rate of baseband processing is 30.72 MHz). The DSP operations include but are not restricted to Fast Fourier Transforms (FFT) and Multiple Input Multiple Output (MIMO) Detection. The existence of these DSP operations would consume much more power and require a larger battery. For handheld equipments and consumer electronics products, lowering the power consumption and computational complexity of DSP operations in mobile stations is of significant importance.The other chanllenge lies in the support of multiple mode and multiple standards. The applications of LTE cannot prevent the existence of 3G standards such as WCDMA and TD-SCDMA. Thus, supports of both 3G and B3G standards would be requiremtns to next generation mobile stations, and how to enable multiple standards supports is one of the design chanllenges. Digital Front End (DFE) is an essential part in all current multiple standards mobile station architectures, and is one of the most open issues when design a multiple standard mobile station, because it works in the highest rate and comsumes lots of computation.In order to solve the above problems, this dissertation studies on the DSP of LTE downlink receivers and investigates its VLSI implementation. This dissertation starts from finding the most computation-harvest bulding blocks in the system, optimizes them and proposes a system approach to enable the Quality-Computational Complexity Scalability to the system. DFE is the bridge between RF/Analog Front End and Baseband Processor. It accomplishes the following functions, such as Sample Rate Conversion (SRC), channelization filtering, matched filtering and so on. It is important module in multiple standard mobile stations because of the intensive computation and diversity of operation. A low computational complexity, multiple modes DFE support 3GPP LTE, WCDMA, and TD-SCDMA is studied in this dissertation. The contributions include a computational complexity oriented SRC factorization methods and efficient matched filtering of LTE PSS. Via the improved SRC factorization, the SRC and channelization part saves 40% computations complexity compared with those using a conventional factorization. The abundancy property of PSS (Zadoff-Chu sequence in frequency domain) is proven, and efficient matched filters are proposed which can save more than 63% complex multiplications and 46% complex additions.The FFT/IFFT processor is the key block in MIMO-Orthogonal Frequency Division Multiplex (OFDM) systems. It does the OFDM modulation and demodulation, and has effect on the power and cost of the chip. A R23 and R24 mixed radix 4-path parallel Delay Feedback pipline 128-2048-point FFT/IFFT processor is studied. The author also improves the multiplier-less Twiddle Factor multiplication method used in parallel FFT/IFFTs. Using computer aided optimization, the impoved mehod can use less constant mulpliers to complete the twiddle factor mulitplications, and FFT/IFFT processor adopting this method outperforms the published results.MIMO is the key technology in next generation wireless communcations. The low power algorithms and chip implementation methods of MIMO detectors are studied. The restricting factors of throughputs and energy efficiency are found. The author improves the Metric-First MIMO detection algorithm by emable pre-termination and a novel enumeration method. Via the novel enumeration, Partial Euclid Distance (PED) is computed by accumulation of PED increments. Because computation of PED increments is much smaller than direction calculation, algorithm propsed by this dissertation save more tha 20% computational complexity than conventional ones. While VLSI implementing, the author designs priority dual queue based on pipeline interval heap and optimize timing of MIMO detection, and obtain a significant results compared with published works.Quality-Compuational Complexity (Q-CC) Scalable signal processing is a recently developing technology, which enables system to. get a balance between energy and quality. In the last part of this dissertation, the author researches the Q-CC scalable DSP systems, and develops a Q-CC scalable LTE downlink receiver. This receiver adopts a control method based on evaluation of equivalent noise contribution. Simulation shows that channel estimation and MIMO detection in this receiver can save more than 30% computational complexity.