Study On Design Techniques Of A SRAM-based Field Programmable Gate Array

In the twenty years since their introduction, Field Programmable Gate Arrays (FPGAs) have become one of the most popular implementation media for digital circuits. In this thesis we aim at exploring a space of architectures and designing a FPGA device according to acquired architecture parameters. Main works and contributions are outlined as follows.Firstly, the frame of FPGA is constituted through analyzing the commercial FPGA devices, with the LUT-based logic cells and symmetrical array routing architecture adopted. LUT-based logic cell has very simple routing demands, which is efficient for logic implementation.Secondly, we investigate the architecture of logic cells in FPGAs. Based on Rent's Rule, the number of logic blocks required to implement given logic circuit versus K is predicted, then an area model of LUT-based FPGA is proposed. The effect of K on FPGA performance is evaluated by comparing the delay of an arbitrary N to 1 logic that has been mapped onto those different K-LUT FPGAs. The effects of two positioning of the pins on the logic block (full perimeter and top/bottom pin positioning) on routing area are analyzed by CAD experiments, and the number of physical locations for each logic block pins is determined. In the FPGA device sample, we adopt 4-LUT-based logic cell with full perimeter pin positioning and one/two physical pin for each logical input/output pin.Thirdly, we investigate global routing architecture. Directional and regional differences on routing channels are analyzed by CAD experiments, and the conclusion of making all channels the same width is drawn. Wire length estimation techniques are studied which is correlated to FPGA routing channel design. We find the causes of low estimation precisions of Donath and improved Donath technique, and propose an improved wire length estimation in which external interconnections are considered. Compared to that of Donath and improved Donath techniques, the error of new algorithm has been decreased by 29% and 5% respectively. A model to predict routing channel width based on total interconnection length is established. Compared to that of Gamal model, the average error of new model has been reduced by 12.5%/6.75% without and with external interconnections. And the channel width of FPGA device sample is determined according to the channel width model.We investigate detailed routing architecture. The conclusion of using multiplexerrouting switch in input connection block and point-to-point routing switch in output connection block is drawn. Routabilities of three normal switch blocks are analyzed using the knowledge of discrete mathematics, the effects of three switch blocks on FPGA area and delay are evaluated by CAD experiments. Wilton switch biock is used in the FPGA sample. A new Monte-Carlo based approach is proposed for FPGA detailed architecture research in which benchmark circuits are not used, and the method is carried out quickly and efficiently.Then, we investigate physical design techniques of a FPGA sample. Programmable routing resources including short, long and hard interconnections are explored. Global clock distribution network, programmable 10 cell and programming architecture have been designed. And the layout design and fabrication of FPGA sample have been completed.Finally, we investigate the test method of FPGAs. Testing a FPGA includes not only exploring and application of test vectors but also generating and configuration of test circuits. Testing the defects of a FPGA is completed using dividing and conquering policy. We construct a test structure based on and/or gate cascaded circuit, and generate test circuits and vectors for MUXs and LUTs. Three detecting and seven diagnosing configuring architecture are given, and test vectors for all configuring architecture are explored. Test method of resistive shorts in FPGA interconnections is studied, and the effects of test conditions on test results are also been analyzed. Functional testing of a FPGA is investigated by implementing a full adder in it.