Specialized Multiplier Circuits

This document presents an n-bit dual recoded squarer and a 2n-bit dual recoded radix-4 squarer as well as an n-bit and 2n-bit integer radix-4 multiplier circuits using dual recoded radix-4 squarers. The radix-4 dual recoding squarer reduces the number of bit product terms employed in the previously known squaring methods obtained by either Booth radix-4 recoded multiplication or by radix 2 squaring. Employing the dual recoded radix-4 procedure for design of a squaring circuit introduces a significant reduction in power and area. Architecturally, radix-4 dual recoded squaring uses only the 1's complement representation which allows for a simpler PPG structure as compared to the 2's complement representation required for Booth radix-4 multiplication. Based on the above squarer, an n-bit radix-4 multiplier is designed to reduce power and size compared to using a traditional multiplier circuit while a similarly designed radix-4 2n-bit multiplier can be used for a gain in area. Finally, an architecture for a combinational floating point multiplier and squarer is described for the purpose of producing a low power floating point square with small area requirements. In order to take advantage of the squarer power improvements with a minimal increase in area, the multiplier and squarer are combined into one circuit. Shared circuitry among the units provides justification for inclusion of a dedicated squarer since a small amount of additional circuitry is required and the power savings for squaring computations is significant as compared to the use of a general-purpose multiplier to generate a squared value.