| This dissertation deals with techniques of a fast and accurate simulation tool for digital integrated circuits composed of metal-oxide-semiconductor (MOS) transistors. The demand for high performance and accuracy of digital logic simulation has led to the development of a logic simulator that is capable of handling two levels of models; gate and switch. This mixed-level approach attempts to high performance, approaching that of a gate-level simulator (by using logic gate models) and switch-level accuracy, by developing a new algebraic structure to handle gate- and switch-level models in a consistent way.; A digital MOS integrated circuit is described as an interconnection of nodes, switches, and logic gates in a mixed manner. This MOS network is partitioned into a set of logical MOS gates and bidirectional switch-level subnetworks (BiNets), which are externally unidirectional. The signal at each node is represented in terms of levels and strengths. The signal levels consist of three values; 0 (low), 1 (high), and X (unknown or invalid). Two driving impedances of a node, from the power nodes of VDD and GND, form a pair (SVDD, SGND) to represent the signal strength at the node, in which SVDD and SGND {dollar}in{dollar} (0, {dollar}infty{dollar}) {dollar}cup{dollar} {dollar}{lcub}rm x{rcub}{dollar}; and x denotes an unknown or invalid impedance value.; Over the signal strength, a new algebraic structure, consisting of two algebras at the gate- and switch-level, is developed to consistently deal with signal strength values of logical MOS gates and BiNets with linear switch-level accuracy. Based on the algebras, two evaluation algorithms are developed for mixed-level simulation. One gate-level evaluation algorithm deals with a logical MOS gate and computes two driving impedances from the power nodes to the output node. For BiNets, the other evaluation algorithm, at the switch-level, provides the signal strength at each node, which is comprised of the driving impedance values of the two shortest paths between the node and the power nodes.; The models and algorithms, presented in this dissertation, have been implemented in a simulation tool, called MIXMOS. With the simulation results so far, the performance, in accuracy and computation cost, of MIXMOS meets with our expectations, namely; (1) linear switch-level accuracy to resolve the MOS peculiarities of bidirectional pass transistor logics, sneak paths, dynamic storage, ratioed logic, clock skews, and driving capability, etc., and (2) noticeable savings in space requirement and computation cost. |
