| Drain engineering issues for the deep submicrometer Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) devices have been extensively explored from the device perspectives, including short channel behavior, driving current, source/drain series resistance, impact-ionization phenomenon, and hot-carrier-induced device degradation, and from several material's perspectives, especially metal silicide processing. Several variations of Lightly-Doped-Drain (LDD), quarter-micrometer NMOSFET devices with effective channel lengths down to 0.18 $mu$m have been designed, fabricated, characterized, and analyzed to assess the technological options and best designs.;The LDD-type drain structure was optimized by extensive process and device simulations using a quadratic response-surface-model derived from a Box-Behnken type Design-Of-Experiment (DOE). The saturation current, the off-state current, and the maximum substrate current were treated as figure-of-merits for tradeoffs between device performance, device short channel effect and device reliability. From the response surface model prediction, the tab length should be small to improve the driving capability, while the tab dose should be high to minimize the sensitivity of the driving capability to spacer formation process variations, and the source/drain junction depth has to be deep enough for a reliable silicide contact. Quarter-micrometer devices were fabricated using different drain engineering parameters and the device electrical characteristics were examined. A driving capability over 500 $mu$A/$mu$m has been achieved for an effective channel length of 0.18 $mu$m, along with good turn-off characteristics. The measured electrical characteristics were consistent with the device simulations. The high driving current was largely attributed to an ultra-low extrinsic series resistance of less than 200 $Omega$-$mu$m achieved by using a novel near-epitaxial CoSi$sb2$ technology with only about 300A silicide in a 0.1 $mu$m heavily doped junction.;The strong dependence of the impact-ionization-induced substrate current on the power supply voltage explains the technological trend to use more heavily doped drain structures without concerns of the hot carrier reliability. Experimental data shows that lowering the LDD tab concentration can only suppress the substrate current in a linear scale, while reducing the power supply can suppress the substrate current more effectively in an exponential scale. With a continuously decreasing power supply from quarter-micron technology and beyond, hot carrier reliability is becoming less of an issue. The challenge ahead would be to create a drain structure that is shallow enough not to deteriorate the channel electrostatic integrity of the miniaturized device while maintaining minimal intrinsic and extrinsic series resistances to maximize the device performance. |
