Modeling and characterization of substrate resistance for deep submicron ESD protection devices

As device dimensions continue to shrink, higher current densities and lower voltage tolerances make ESD, or Electrostatic Discharge, an increasingly important issue to guard against for ensuring reliability. Industry data show that one-third of all customer returns are due to ESD.; IC chips are protected against ESD by on-chip protection circuits, which are connected between the I/O pads and the internal circuitry. The protection circuit, which consists of protection devices, is designed to rapidly discharge high current in an ESD event.; Typically, the design of ESD protection circuits is an empirical approach. Several candidate circuits are fabricated, characterized, and evaluated for key physical and performance parameters using known testing techniques. Different combinations of device geometries and process technologies are evaluated until a suitable circuit with the desired characteristics is found. This resource intensive design approach clearly motivates a simulation based solution which enables quicker turnaround as well as obvious cost-savings in materials and resources.; The focus of our research is on modeling and characterizing ESD protection devices, especially the substrate resistance, in a state-of-art CMOS technology. Unlike normal MOS operation, both the channel and the substrate region in a given device need to be modeled to show that current extends from the channel into the substrate under ESD stress. We begin by developing a circuit model to simulate the high current characteristics under ESD stress since none exist in commercial circuit simulators. We then demonstrate the extraction of circuit-level parameters from experimental data using a systematic extraction methodology.; The next phase of our research extends the circuit model to enable simulation of different layout and process variations by focusing on modeling substrate resistance. Substrate resistance determines the on/off state of the protection device by providing current discharge paths from drain to substrate and drain to source. This parameter also captures the substrate interactions of different protection circuit elements.; In order to address the sensitivity of substrate resistance to layout and process variations, we propose a new methodology called quasi-mixed-mode (QMM) device and circuit simulation approach, and we will describe the QMM approach in detail as well as illustrate the application of the model to the modeling of substrate resistance for deep sub-micron ESD protection nMOSFETs. The substrate resistance simulated by this method shows good agreement with the values extracted from experimental data. This technique can be employed to simulate turn-on characteristics of ESD protection devices and determine the impact of process and layout variations on their reliability before fabrication of the actual devices.