Process Improvement To Enhance HV PMOS Drain Breakdown Voltage

CMOS process technology, which is based on the MOSFET device, is the main stream in today's integrated circuits technology and now over 80% Integrated Circuits product are designed and fabricated by CMOS process technology. Today, CMOS process technology have already evoluted to sub_micro era and even to deep sub-micro era CMOS process technology. In the sub_mirco and deep sub_micro CMOS technology era, we should consider the threshold voltage, saturation driving current, leakage current of MOSFET meeting the application requirement of detail circuit in the design, and more we should consider another key limited factor: the drain breakdown of MOSFET, which is usually called gate-controlled drain breakdown for its breakdown voltage is highly effected by gate voltage.So when we design a detail circuit in the integrated circuits with some MOSFET, we need not only ensure the MOSFET's basic electrical parameters: such as threshold voltage, saturation driving current and leakage current fit our requirement. But also ensure a suitable drain breakdown voltage. For example, when we design the I/O signal ESD protection circuit and power-in pad ESD protection circuit for the integrated circuits, we should design a MOSFET with suitable drain breakdown for the key protection elements to make them turn on at the right condition timely and uniformly, so we can protect the devices in the core circuits of integrated circuits; Another example in the FLASH memory, we need high operation voltage over 10V for basic flash cell writing and erasing operation, so we need design a high drain breakdown voltage MOSFET to realize the periphery writing and erasing circuits.So how to design a MOSFET with suitable drain breakdown voltage to meet the application requirement for the detail circuits in the integration circuits after we deeply understand the drain breakdown mechanism of MOSFET is very important. This thesis is written for that we need design a HV PMOS with–12V drain breakdown voltage to meet the application requirement in the detail circuit of our company's FLASH product. In this thesis, I describe the three types drain breakdown mechanism in current lightly doped diffusion source and drain structure (S/D LDD) MOSFET and their determination method, then describe a process improvement to enhance the drain breakdown voltage which can be implemented in the mass production in industry: to enhance the drain breakdown voltage by enhancing LDD implant dosage, tilting the implant angle and discarding the post LDD implant RTA, and analyze the mechanism. And more, this thesis describe the process improvement's impact to HV PMOS'others electrical parameters, at last we re-evaluated the device reliability after the process improvement.