| This dissertation investigates the design techniques of low-voltage, power efficient switched-capacitor delta-sigma modulators intended for audio applications (i.e., 16-bit resolution at a 20kHz signal bandwidth). First, it presents highly accurate integrator models which can be used in the early design phase in order to reduce the power dissipation of delta-sigma modulators. Based on these models, this research proposes methods of improving the power efficiency of low-voltage modulators without sacrificing the performance.; A prototype demonstrating the presented techniques was designed and fabricated in a 0.5{dollar}mu{dollar}m triple-metal single-poly n-well CMOS process, having NMOS and PMOS threshold voltages of +0.60V and {dollar}-{dollar}0.80V, respectively. The presented delta-sigma modulator operates from a single 1.5V supply. A novel fourth-order single-loop topology with low internal signal swings is introduced. The modulator is realized with fully-differential stray insensitive switched capacitor integrators. The first stage employs a two-stage Miller amplifier whereas the remaining three stages employ a single-stage folded-cascode amplifier. Both amplifiers have PMOS input differential pairs and the input common-mode level is set to 0.3V for proper operation at 1.5V. Clock bootstrapping circuits are utilized to boost the clock signals in order to facilitate the low-voltage operation of switches. Careful capacitor scaling, taking advantage of the noise shaping of the nonidealities of the inner stages, and the use of a non-50% duty-cycle clock period are among the few techniques applied to reduce the power dissipation. The presented delta-sigma modulator when clocked at 2.8224MHz, in a 20kHz bandwidth achieves 98dB dynamic range while consuming only 1mW. More than 80% of the total power is due to the first integrator. The peak SNR and SNDR are 89dB and 87dB, respectively. |
