A design methodology for addressing cross talk in integrated circuits

This dissertation focuses on a design methodology for addressing capacitive crosstalk. Crosstalk is a severe problem in the field of VLSI design where aggressive scaling of interconnect pitch has led to increased capacitance between adjacent traces, causing non-linear interactions evidenced as timing violations and erroneous circuit activity. New process technologies will achieve tighter metallization, increased clock frequencies, smaller voltage swings and longer interconnect. Estimates show these trends will double the impact of crosstalk during the next decade.;A physical design methodology that accounts for crosstalk with accurate and consistent estimates of wiring constraints throughout the design flow is presented. By maintaining a consistent view across the design flow, violations due to crosstalk become predictable, and therefore, avoidable. A case is made for estimating crosstalk using an empirical model, avoiding crosstalk using congestion-driven placement, and reducing crosstalk via a global-route embedder.;Accurate models for crosstalk interactions are required to achieve timing convergence. A computationally efficient empirical model for crosstalk impact that captures noise and delay-changes on coupled conductors is presented. It permits a performance-driven approach that is superior to the popular method of minimizing adjacent capacitance for addressing crosstalk. Simulations show the model to be accurate within 8% for wire-delay and 10% for noise.;A strong correlation between crosstalk and wiring congestion is demonstrated. Experiments on designs ranging from large standard-cell groups to a microprocessor show a majority of the critical nets have more than 50% of their length passing through regions of high congestion. Through interplay between a wiring-engine and quadratic placement, a global treatment of congestion is demonstrated. Experiments show up to 20% improvements in the wireability of designs.;A new method for mitigating the impact of crosstalk, route embedding, is presented. It simultaneously modifies a set of route structures to satisfy timing and noise constraints while maintaining routing constraints. Linearized crosstalk constraints are derived and satisfied for the expected noise and wire-delay at critical sinks. This is achieved by computing new spacings and inserting ground shields. Routing capacity constraints are enforced to guarantee a detailed routing solution. The methodology results in embeddings that satisfy a range of crosstalk constraints for all test cases.