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Self-clocked field programmable gate arrays for exploratory design

Posted on:1999-08-11Degree:Ph.DType:Dissertation
University:Stanford UniversityCandidate:How, Dana LivingstonFull Text:PDF
GTID:1468390014968065Subject:Engineering
Abstract/Summary:
Before Field Programmable Gate Arrays were developed, the lengthy fabrication delays and large one-time costs associated with gate arrays and semi-custom design were seen as the major obstacles to exploratory design. Although the many FPGA architectures introduced over the last decade have succeeded in eliminating these obstacles, these architectures and their supporting CAD tools still do not fully support exploratory design: typically the CAD tools take far too long to map a design into a larger FPGA, or to partition and map the design into several FPGAs, for the logic designer to enjoy the interactive design process familiar to users of integrated software compiling and debugging systems.; In this research, we present a new FPGA more amenable to exploratory design. This FPGA includes SRAM-based configurability to support rapid reprogrammability, regular segmented routing channels more easily and rapidly routed than the interconnect architectures seen in commercial SRAM-based products and a self-clocked architecture that eliminates clock distribution problems and facilitates the composition of multiple FPGAs. Although each of these features in isolation imposes a notable area penalty, we argue that their combination results in an improvement in flexibility, usability and performance at an acceptable cost in area for rapid prototyping, compared with other architectures.; We present an overview of eight separate FPGA designs incorporating these ideas, focusing on four fabricated by MOSIS and measurements of their performance. The final test chip is a complete FPGA comprising a 6 x 4 array of configurable logic modules, segmented routing channels with partially depopulated switches at track intersections, a configurable I/O ring and an integral controller for various programming, testing and single-step modes.; Finally, we address the various CAD tool improvements that will be needed to make an exploratory design system based on this FPGA feasible, as well as showing that the specific optimizations we have developed, unique to this work, do not decrease routing flexibility.
Keywords/Search Tags:Gate arrays, Exploratory design, FPGA
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