| MIMD parallel architectures demand efficient interprocessor communication to maximize system utilization and performance. By 2012, the National Technology Roadmap for Semiconductors projects a factor of 25 decrease in the number of off-chip signal I/Os per transistor, and in gigascale VLSI systems interconnects will dominate chip cost and performance. To meet future demands, these interconnect signals must communicate at significantly higher speeds while operating more efficiently to meet system size, weight, power, and energy requirements. These design pressures favor high-bandwidth serial channels for interprocessor communication. This dissertation research addresses mechanisms for efficient interprocessor communication over serial channels including flit-level hop-by-hop error control in wormhole-switched networks and the HiPER routing element. Flit-level error control reduces the effective bit error rate of the system, allowing channels to run at lower energy per bit while operating within system error rate requirements. Flit-level error control provides greater than two decades improvement in effective bit error rate. HiPER is an efficient high-performance router implementing flit-level error control and mad postman switching over serial channels. This router has been implemented and studied to determine the impact of combining flit-level error control and serial channels in a low-latency router. In the target architecture for HiPER, it consumes 33% less silicon area than a comparable parallel crossbar router, and it delivers 33% lower message latency. |
