Design for testability techniques and optimization algorithms for performance and functional testing of multichip module interconnections

The objective of this research is to drive down the cost of functional testing of multi-chip module (MCM) interconnections before assembly of ICs using single probe test technique and to devise a formal design for testability (DFT) strategy for MCM interconnect performance test and diagnosis after assembly. Testing of MCM interconnections has become an activity of critical importance and considerable difficulty in the MCM design and test process in view of the demand for high performance and high density of packaging. First, electrical testing of a bare MCM substrate interconnections using a single probe is considered. A tight bound on single probe testing time is computed using rigorous theoretical analysis. Efficient and practical heuristic algorithm for finding an efficient probe route, to optimize the total test time of an MCM substrate, is presented. Experiments on the benchmark MCM netlist show that a up to 40% reduction in single test probe traversal time can be achieved by using the proposed algorithm. Secondly, a formal DFT methodology for comprehensive performance testing of assembled MCM interconnections is presented. A novel distributed BIST architecture is proposed to test and diagnose key performance issues such as the effects of cross-talk ground bounce and simultaneous switching noise. The technique consists of specialized and reconfigurable on-chip precharacterized test pattern generators and multiple input signature registers. It is proved that interconnections switching activities can be effectively recreated and an accurate distributed diagnosis can be performed with low area overhead. The algorithms developed in this research are integrated into a CAD tool to automate MCM interconnections test flow.