| Bandgap engineering of silicon using silicon-germanium (SiGe) is widely popular for boosting the performance of bipolar and CMOS transistors. Several research groups have successfully demonstrated modulation-doped FET (MODFET) structures for enhancing the pFET performance, to make it comparable to the nFET's. This results in symmetric CMOS devices, with a large potential for area savings. With the recent market boom for wireless and portable communication systems operating in the 2-10GHz frequency range, the emphasis on future technologies has shifted to devices not only with high performance and high integration, but most importantly with good microwave substrate qualities. Gallium-arsenide, with its semi-insulating substrate, is a possible, but costly alternative. A silicon alternative is to use a silicon-on-sapphire technology, which combines excellent CMOS devices with a good microwave substrate. The recently introduced CMOS on thin-film silicon-on-sapphire (SOS) technology is well-suited in such applications where high-Q on-chip inductors are needed in addition to high-speed CMOS. This dissertation takes the thin-film SOS technology a step further by integrating it with SiGe MODFET technology, to form a SiGe CMOS on SOS technology. In this case, a strained-SiGe layer on a relaxed-Si structure is used to enhance the mobility meff , transconductance gm , and cutoff frequency fT of the pFET's. This dissertation presents the fabrication, electrical characterization, profile optimization, and radiation response of SiGe pFET's on silicon-on-sapphire (SOS) technology. The results show that the SiGe pFET's have higher low-field mobility meff , transconductance gm , and cutoff frequency fT than comparably constructed Si pFET's. At low temperature (85 K), a secondary peak is observed in the linear gm of the SiGe pFET's, and is attributed to hole confinement in the SiGe channel. A low-frequency noise study shows significant improvement in the SiGe pFET's, and is attributed to a lower sampling of interface trap density caused by the band offset at the oxide interface due to SiGe. Drain-induced back-channel inversion (DIBCI) is shown to occur in short gate length devices, resulting in high off-state leakage current conduction at the back Si-sapphire interface. A novel structure is proposed which optimizes the threshold voltage, maximizes hole confinement gate voltage range, and cutoff frequency, while at the same time minimizes the effects of DIBCI to make the design usable at gate lengths as short as 0.25 m m. Finally, the response to high energy gamma-irradiation of these devices is studied using a cobalt-60 gamma source. The nFET's are shown to be robust up to 1Mrad total dose. In the pFET's, however, a novel leakage phenomena is seen due to radiation-induced back-channel inversion, which is attributed to trapping of electrons at the back Si-sapphire interface. |
