| The goal of this work was to research, design, implement, test and evaluate high speed serial communication circuits. Research involved an in-depth study of the state of the art in high speed digital and analog circuits, SiGe technology, and serial communication circuits. Three prototype 20 Gb/s transceiver chips were designed using current mode logic (CML) bipolar logic families and IBM's SiGe 0.5 μm heterojunction bipolar transistor (HBT) technology. Two designs were fabricated and extensively tested, and test results were compared to simulation results.; The optimized second prototype operated at speeds in excess of 20 Gb/s. It utilized a patent pending novel four stage feed-forward interpolated ring voltage controlled oscillator (VCO) architecture. By feed-forwarding every stage's output by one stage the architecture improved the core frequency by more than 33% and produced a phase noise of −90.2 dBc/Hz at I MHz. The transmitter took advantage of the phase quadrature nature of the VCO in the novel 2-to-1 symmetric multiplexer. This multiplexer had full input to output symmetry on all three inputs and was capable of performing output data retiming. The PLL had a wide bandwidth of 6 MHz, to suppress VCO noise, and produced in-band jitter of 2.0 ps from 100 kHz to 100 MHz.; The receiver utilized the full eight phases of the VCO to twice oversample every data bit. Four bits of data were sampled through the phase detector (PD) and a 4-to-16 demultiplexer produced 16 bits of parallel data. The PD was capable of extracting timing information from every transition. The loop filter incorporated a negative impedance charge pump which exhibited excellent performance.; A third prototype was developed, but not fabricated, using the data acquired from the first two designs. The transmitter PLL was optimized to account for the phase noise of the VCO. A frequency detector was added to the PLL to increase the pull-in range. The loop filter was also modified to use a negative impedance charge pump. In addition, the receiver PLL was optimized to improve the bit error rate. |
