| Serializer and Deserializer circuits (SERDES) are important building blocks for communications systems in both long distance optical networks as well as for high speed connections over distances as small as the length of a circuit board. The focus of this work is in the area of high speed SERDES, particularly in the area of serial transmitter circuits which allow high data rates with respect to fundamental limits inherent in device parameters such as fT and fmax. Using the IBM SiGe 5HP 50GHz fT/fmax BiCMOS process and CML logic, our earlier designs achieved 20Gbps data rates. SiGe was chosen for its low cost to performance ratio, but the design architectures are not process specific. All our designs are monolithic, relying on no external tuning components and feature internal VCOs. The high rate of operation is made possible by using quarter-rate multiphase clocks and novel multiplexer architectures which reduce the need for final retiming. These designs were fabricated and tested and the results compared with simulation. Newer architectures subsequently developed have shown promise for even higher speed operation in the same process. A completely new transmitter chip has been designed, incorporating an internal pseudo-random number generator, a novel 16-to-4 multiphase multiplexer, and an entirely new final 4-to-1 edge steering multiplexer architecture (ESMA). The 16-to-4 multiplexer addresses difficult design constraints on the synchronization of multiple clock phases along with those phases after having passed through clock dividers. The ESMA 4-to-1 multiplexer allows the generation of a serial stream in a symmetrical manner using four quarter-rate clock phases. Heavy emphasis was placed on optimization for speed and symmetry in order to produce the highest rate output. A new test chip with 1825 HBTs using these designs has been fabricated and tested up to 27Gbps. A second improved prototype has also been designed, and simulation results indicate the potential for greater than 30Gbps operation, with some corresponding reduction in output quality. This improved prototype has not yet been fabricated, but it is planned for in the future. |
