CMOS power amplifiers for wireless communications

Linearity and efficiency are the two most important characteristics of power amplifiers (PAs) for wireless applications. In this dissertation, we investigate three topics on CMOS power amplifiers: class-E, class-AB, and dynamic biasing technique.; Previous analytical efforts on class-E power amplifiers assumed either zero switch resistance and/or infinite drain inductance, leading to a less optimized design. In this dissertation, we developed an improved design technique by accounting for both finite drain inductance and finite “on” resistance for a CMOS device. A design example based on the developed algorithm achieves an output power of 0.25 W and a drain efficiency of 87% for a 3.5 mm NMOS class-E device with V_DD = 2 V and f_c = 1.90 GHz.; The intrinsic linearity obtained in a CMOS class-AB operation is often insufficient to meet the stringent linearity requirement imposed by modern wireless standards. In this dissertation, we propose a capacitance compensation technique to improve PA linearity. Experiments show that the compensation technique can improve both the two-tone, third-order intermodulation (IM3) and adjacent-channel leakage power (ACP) by approximately 8 dB. While meeting the 3GPP-WCDMA ACP requirements, the linearized two-stage amplifier is capable of delivering an output power of 24 dBm with a small-signal gain of nearly 24 dB and an overall power-added efficiency of 29%.; The designed two-stage CMOS class-AB power amplifier suffers serious efficiency degradation when operated at low output power levels. In this dissertation, it was demonstrated that a dynamic biasing technique can improve the average efficiency of a CMOS class-AB power amplifier by controlling the gate bias voltage with the envelope of the input RF signal. However, the envelope signal introduced by the dynamic biasing technique can significantly limit the overall linearity of the CMOS class-AB PA. Both analysis and experiments show that the dynamic biasing technique can significantly degrade the IM₃ and ACP performances of the designed two-stage CMOS class-AB power amplifier.