Hierarchical synchronization scheme for structured VLSI systems

As the VLSI technology improves, the impact of clock skew and interconnection delay are significant on the system performance and the design turn around time. The technology advance drives rapid increase of design complexity of systems implemented on a single chip. In addition, the timing problems caused by the clock skew and significant interconnection delays have become impediments in efficient VLSI system design. Solving these problems at a low level of design hierarchy alone can lead to the explosion of the problem size.; Hierarchical design method is a common approach in VLSI designs, in which complex functions to be implemented are divided into less complex sub-functions. Similarly, synchronization scheme for complex VLSI system is divided into two levels by a module interconnection scheme called "self-timed mesochronous interconnection". This scheme allows a single large clocking region being partitioned into several independent clocking regions during the functional subdivisions. The interconnection scheme is modeled as a digital communication structure and is implemented according to asynchronous design principles. The resulting systems are not strictly synchronous nor asynchronous but have a similar structure to those used in mesochronous digital communication.; In this research, the difficulties of clock distribution for structured VLSI design were reviewed and other hierarchical synchronization schemes were examined. The main ideas in realizing two-level synchronization are described by means of a system model. Two modes of module interconnection were then developed. These module interconnections consist of a self-timed FIFO and a data arrival control (DAC) unit. The operation of the two components were analyzed and associated design requirements were determined. A hypothetical technology scaling from a MOSIS 0.5{dollar}mu{dollar}m technology to 0.1{dollar}mu{dollar}m was carried out and a high speed dynamic logic style called "Buffered Single-Phase Clocking" logic was developed in order to perform the experiments using the 0.5{dollar}mu{dollar}m technology. Module interconnection model is derived from the design of a 800MHz bit-level pipelined discrete cosine transform chip in a 0.5{dollar}mu{dollar}m technology. The subcomponent size and interconnection length in this model can effectively represent the modules and their interconnections of a system in 0.1{dollar}mu{dollar}m technology, where the impacts of clock skew and interconnection delay can be clearly observed. Experiments on unidirectional interconnection and signal joining case show that the proposed scheme is immune to the clock skew and interconnection delay. The research results presented in this dissertation provide a good realization of hierarchical synchronization scheme without sacrificing performance, while maintaining the synchronous design style.