Testing System For Mimo-ofdm Synchronization Algorithm For Vlsi Implementation

The basic idea of OFDM technique is to divide the available bandwidth into a number of subcarriers. Instead of transmitting the data symbols in a serial way, OFDM transmitter partitions the original data into blocks of data symbols transmitted in parallel. By doing so, the duration of OFDM symbol can be made long when compared to the channel delay, and the bandwidth of each sub-band can be made small when compared to the coherence bandwidth of the channel. Thus, the data of each sub-band will experience flat fading instead of frequency selective fading, which reduces the complexity of channel equalizer. The basic idea of MIMO technique is to utilize multiple antennas to accomplish multiplexing gain and/or diversity gain. The system we build is used to investigate the basic principles that can apply MIMO-OFDM technique to a specific channel environment, of which the impulse response is fast changing. The aim of the system is to get a spectral efficiency higher than 3 bit/s/Hz. On the overall OFDM-based system performance, the performance of the frequency and timing synchronization is of major influence. This paper is focused on developing the timing and frequency synchronization algorithms for MIMO-OFDM systems as well as their specific VLSI architecture.On the first part of the paper, the method of converting intermediate frequency signal to its equalized baseband signal is discussed. In order to implement that conversion, a Digital Down Converter is designed. This converter needs an anti-overlapping filter with a relatively high order, which means the large area of digital circuit to implement it. To lower its complexity, a creative filter structure is proposed.In the timing synchronization part, this paper analyzes various methods about setting the threshold for a specific timing synchronization detector. A method which can be used effectively under an environment with high SNR dynamic range is chosen for the detector. The timing synchronization detector works before frequency synchronization estimator, which means the timing synchronization detector maybe work under carrier offset. A structure of timing synchronization detector is proposed to enhance its detection probability under carrier offset. To meet the requirement of channel estimation that the timing synchronizer must synchronize the first path, a detector structure is proposed. The VLSI architecture of each of these detect proposed is designed and implemented by Register Transfer Level code.In addition to timing synchronization, frequency synchronization is also crucial for the transceiver design. This paper designs a frame structure for a frequency synchronization algorithm, and proposes a VLSI architecture for that synchronization estimator.To verify the effectiveness of each of these VLSI architectures, this paper thoroughly introduces the verification process and its results. The verification results show that the timing and frequency synchronization algorithms can be used on practical system while meeting the precision requirement of MIMO-OFDM algorithm.