IC performance prediction for test cost reduction

In today's competitive semiconductor manufacturing industry, it is very important to reduce cost and time-to-market and increase product yield with effective process control. After fabrication, integrated circuits (ICs) are tested while still in wafer form, and then again after they have been packaged. These are referred to as wafer and final test. In addition, electrical test structures such as ring oscillators and individual devices on the wafer are tested to determine electrical parameters. Final electrical test of packaged chips for specified performances is more expensive than wafer level test. The tested performances include operating voltage, temperature range, and speed.;The goal of this research is to build a model predicting IC performances as a function of wafer electrical parameters. Electrical test structures on the wafer will be designed to obtain wafer electrical parameters. These test structures can be either sensitive to the given performances of a circuit or indirect measurements of process parameters highly correlated to performances. If we can predict the performance of integrated circuits accurately enough based on a few tests, we may be able to eliminate additional tests, such as several temperature tests or voltage tests. Ideally we can use low-cost tests to eliminate high-cost tests to reduce overall test cost. These predictions can also be used for process diagnosis to improve manufacturability and for start bin selection to reduce average test time.;Our model-building methodology uses a simulation-based approach in conjunction with measured data. We use process and device simulations by pdFab and circuit simulation by HSPICE. PdFab is a simulation environment that makes use of process and device simulators such as SUPREM, to model how process variations impact device performance. The simulations are executed on an experiment plan and stepwise regression is used to build model equations without insignificant terms.;The modeling methodology, is evaluated with wafer test data for an industrial microprocessor to predict critical path delays and it is also applied to a benchmark circuit in order to reduce temperature tests.